Various arrangements for performing vector-matrix multiplication are provided here. Digital input vectors that include binary-encoded values can be converted into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs). Using an analog vector matrix multiplier, a vector-matrix multiplication operation can be performed using a weighting matrix for each bit-order of the plurality of analog signals. For each performed vector-matrix multiplication operation, a bit-ordered indication of an output of the analog vector matrix multiplier may be stored. A bit-order weighted summation of the sequentially performed vector-matrix multiplication operation may be performed.

A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), an amplifier, and a conversion circuit. The multiple DACs function in a pipelined manner such that each DAC receives an analog input signal in different cycles of a clock signal and generates a corresponding analog output signal. The amplifier amplifies each analog output signal to generate a corresponding amplified analog signal in different cycles of the clock signal. The conversion circuit successively approximates each analog output signal to generate multiple digital signals. Thus, a digital output signal of the pipeline ADC is generated based on the corresponding amplified analog signal and at least one of the multiple digital signals. The pipeline ADC utilizes one cycle for performing each of sampling, conversion, and amplification operations, which results into low power consumption by the pipeline ADC.

Capacitor arrays and methods of operating a digital to analog converter are described. In an embodiment, a capacitor array includes a unit capacitor (Cu) structure characterized by a unit capacitance value, a plurality of different super-unit capacitor structures, and a plurality of different sub-unit capacitor structures, each different sub-unit capacitor structure having a different capacitance defined by a division of the unit capacitance value.

A DAC (60) is disclosed. It comprises an input port comprising N input terminals p.sub.1, p.sub.2, . . . , p.sub.N configured to receive voltages representing N input bits b.sub.1, b.sub.2, . . . , b.sub.N, respectively, wherein the significance of b.sub.j is higher than for b.sub.j1 for j=2, 3, . . . , N. Furthermore, it comprises a capacitor ladder circuit (100) comprising N capacitors C.sub.1, C.sub.2, . . . , C.sub.N with capacitance C, each having a first terminal and a second terminal. Capacitor C.sub.j is connected with its first terminal to the terminal p.sub.j of the input port. For each j=1, 2, . . . , N1, the capacitor ladder circuit (100) comprises a capacitor (150.sub.j) with capacitance xC connected between the second terminal of capacitor C.sub.j and the second terminal of capacitor C.sub.j+1. The DAC (60) also comprises an input circuit (140) connected to the input port comprising at least one capacitor (160.sub.1-160.sub.N), each connected between a unique one of the input terminals p.sub.1, p.sub.2, . . . , p.sub.N of the input port and signal ground.

An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.

A DA conversion device includes a level determiner determining whether a level of the digital signal or the analog signal is higher than a predetermined threshold value; a DA converter including plural capacitors, an operational amplifier which generates the analog signal, and a plurality of transistors which connects each of the plural capacitors to a first or a second reference voltage according to the digital signal in a first connection state and connects the plural capacitors between an input terminal and an output terminal of the operational amplifier in a second connection state; and a setting part which receives a clock signal and sets gate-source voltages of the plurality of transistors such that the plurality of transistors is in the first connection state in a first period of the clock signal and the plurality of transistors is in the second connection state in a second period of the clock signal.

Methods and systems for performing analog-to-digital conversion is provided. In one example, an analog-to-digital converter (ADC) circuit comprises a leakage compensation circuit and a quantizer. The leakage compensation circuit is configured to: receive an input signal, the input signal being susceptible to a drift due to a charge leakage; receive a reference signal; and generate a leakage-compensated signal pair to compensate for the charge leakage, wherein the leakage-compensated signal pair comprises one of: (a) a leakage-compensated version of the input signal and the reference signal, (b) the input signal and a leakage-compensated version of the reference signal, or (c) a leakage-compensated version of the input signal and a leakage-compensated version of the reference signal. The quantizer is configured to perform a leakage-compensated quantization of the input signal based on the leakage-compensated signal pair to generate a digital output representing the input signal.

A DA conversion device includes a level determiner determining whether a level of the digital signal or the analog signal is higher than a predetermined threshold value; a DA converter including plural capacitors, an operational amplifier which generates the analog signal, and a plurality of transistors which connects each of the plural capacitors to a first or a second reference voltage according to the digital signal in a first connection state and connects the plural capacitors between an input terminal and an output terminal of the operational amplifier in a second connection state; and a setting part which receives a clock signal and sets gate-source voltages of the plurality of transistors such that the plurality of transistors is in the first connection state in a first period of the clock signal and the plurality of transistors is in the second connection state in a second period of the clock signal.

A capacitive sampling circuit comprises: a first-differential-input-terminal, configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal, configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal, configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors, each having a first-plate and a second-plate; a plurality of reference-voltage-terminals, each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block configured to selectively connect the first-plate of each of the plurality of first-sampling-capacitors to either: (i) the first-differential-input-terminal; or (ii) a respective one of the plurality of reference-voltage-terminals; and a first-capacitor-second-plate-switch, configured to selectively connect or disconnect the second-plate of each of the plurality of first-sampling-capacitors to the second-differential-input-terminal.

Apparatus and associated methods relate to unit circuits that having a number of capacitors and/or buffers controlled by two different control signals, capacitors and/or buffers that receiving, through routing, a same control signal from a control circuit are physically placed adjacent without crossing routings that connects capacitors and/or buffers controlled by a different control signal. In an illustrative example, a first capacitor may be configured to receive a first control signal through an inverting buffer, and a second capacitor may be configured to receive the first control signal through a non-inverting buffer, the inverting buffer and the non-inverting buffer may be provided by an integrated buffer structure. By arranging the physical positions of the capacitors and/or buffers, wire capacitances of the unit circuit may be advantageously reduced.