An N-bit type charge redistribution analog-to-digital conversion device includes an input terminal configured to receive an input signal and coupled via a line to an output terminal. The output terminal is configured to be coupled to a comparator. The device further includes three reference potential sources of different values and a network of capacitors, where a first terminal of each capacitor is coupled to the line, and where a second terminal of each capacitor is coupled to switching circuit configured for coupling the second terminal of each capacitor to one of the reference potentials.

A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a first set of scaled capacitors connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to a second set of scaled capacitors configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor of first set of scaled capacitors has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.

The present disclosure relates to a capacitor array for an analog-to-digital converter, a successive approximation register analog-to-digital converter and a capacitor array board. The capacitor array includes a control logic generation circuit, a control code logic conversion circuit, a first sub-capacitor array and a second sub-capacitor array configured to form different regions of a high-order bit region and a low-order bit region. In the present disclosure, the capacitances of the second capacitor units are equal, so that the second capacitor units can be sequentially switched. Thus, no matter which bit in the second binary code changes, it will not cause a large number of the second capacitor units to switch together, thereby reducing conversion error. In addition, the capacitor array is divided in regions, which avoids the problem of a large number of parallel branches in case where only the second sub-capacitor array is arranged.

A stage, suitable for use in an analog to digital converter or a digital to analog converter where the stage comprises a plurality of slices that can be operated together to form a composite output, can have reduced thermal noise, whilst each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance.

A DA converter to reduce second-order harmonic distortion more precisely with convenient configurations. A DA converter including: a DA converting unit to input reference voltage and a digital value and output an analog signal according to the digital value based on the reference voltage; and a superimposing unit to superimpose, on the reference voltage, a superimposing signal based on the analog signal that is output from the DA converting unit, and a DA converting method are provided. The DA converter may further include a setting input unit to input setting regarding at least one of a superimposing amount and a sign of an analog signal to be included in the superimposing signal. Also, an adjusting apparatus and an adjusting method to adjust the DA converter are provided.

A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to the output of a multiplexor configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.

Capacitor arrays and methods of operating a digital to analog converter are described. In an embodiment, a capacitor array includes a unit capacitor (Cu) structure characterized by a unit capacitance value, a plurality of different super-unit capacitor structures, and a plurality of different sub-unit capacitor structures, each different sub-unit capacitor structure having a different capacitance defined by a division of the unit capacitance value.

An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage V.sub.ref=N*VDD, where N<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a supply (VDD), and one or more first capacitors also coupled to a supply (VDD) and associated with at least the MSB, and a plurality of second capacitors coupled to a reference (Vref), where Vref=N*VDD, where N<1, wherein the first capacitor having a capacitive value that is equal to (1N) times the total capacitance of a parallel combination of the one or more first capacitors, the second capacitors associated with less significant bits, and an input voltage line carrying an input voltage (V.sub.IN) signal as the second input to the comparator.

A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to the output of a multiplexor configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.

A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a first set of scaled capacitors connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to a second set of scaled capacitors configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor of first set of scaled capacitors has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.