A calibration circuit, including: a signal generator circuit configured to generate a modulated analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip.

Systems and methods are provided for architectures for an analog feedback class D modulator that increase the power efficiency of the class D modulator. In particular, systems and methods are provided for an analog feedback class D modulator having a digital feed-forward loop. The digital feed-forward loop allows for removal of signal content from an input to an analog-to-digital converter, such that the ADC processes just noise and/or error. Using the techniques discussed herein, the loop filter is low power as it processes error content but not signal content.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

A communication unit (300, 400, 500) is described that includes at least one antenna (302, 402, 502); a plurality of radio frequency (RF) circuits (304, 310, 404, 410) respectively coupled to at least one antenna (302, 402, 502); at least one sigma-delta modulator (316, 416, 616, 816) comprising a number of stages, each stage comprising at least one signal-feedforward coefficient (603, 604, 605), a filter and a feedback gain element, the at least one sigma-delta modulator (316, 416, 616, 816) coupled to the plurality of RF circuits (304, 310, 404, 410) and configured to perform sigma-delta modulation; and a controller (340, 440, 640, 840) operably coupled to the at least one sigma-delta modulator (316, 416, 616, 816). The at least one sigma-delta modulator (316, 416, 616, 816) comprises an input (315, 415, 602, 801, 802, 902) configured to receive multiple multi-phase input signals and the controller (340, 440, 640, 840) is configured to adjust the at least one signal-feedforward coefficient (603, 604, 605) of the at least one sigma-delta modulator (316, 416, 616, 816) when combining the multiple multi-phase input signals.

A loop-filter comprising: a first-integrator, and one or more further-integrators. The first-integrator is an active-RC integrator, and comprises a first-integrator-input-terminal configured to receive: (i) an input-signal, and (ii) a feedback-signal; a first-integrator-first-output-terminal configured to provide a first-integrator-first-output-signal; and one or more first-integrator-further-output-terminals. Each of the one or more further-integrators is a Gm-C integrator, and they are connected in series between the first-integrator-first-output-terminal and a loop-filter-output-terminal. For a first further-integrator in the series, the further-integrator-input-terminal is configured to receive the first-integrator-first-output-signal. For any subsequent further-integrators in the series, the further-integrator-input-terminal is configured to receive: (i) the further-integrator-output-signal from the preceding further-integrator in the series; and (ii) one of the first-integrator-further-output-signals.

A class-D amplifier includes measurement of speaker current via the low-side drive transistors of the amplifier. In one embodiment, a class-D amplifier includes two high-side transistors, two low-side transistors, a first sense resistor, a second sense resistor, and a sigma delta analog to digital converter ( ADC). The two high-side transistors and two low-side transistors are connected as a bridge to drive a bridge tied speaker. The first sense resistor is connected between a first of the low-side transistors and a low-side reference voltage. The second sense resistor is connected between a second of the low-side transistors and the low-side reference voltage. The ADC is coupled to the bridge to measure voltage across the first sense resistor and the second sense resistor.

Various embodiments relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop filter may further include a first summing node having an output coupled to an input of the first integrator. Further, the delta-sigma loop filter may include a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node. The delta-sigma loop filter may also include a first feedback path from an output of the quantizer to a second input of the first summing node.

Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may also include a first summing node having an output coupled to an input of the first integrator, and a feedforward path from an input of the delta-signal loop filter to a first input of the first summing node. Further, each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first feedback path from an output of the quantizer to a second input of the first summing node.

A modulator includes a first integrator which has first and second capacitors and integrates an analog input signal and a feedback analog signal, a second integrator which has third and fourth capacitors and integrates an output signal of the first integrator, a differential amplifier which has input and output terminals switched and connected via a switch circuit to either the first and second capacitors or the third and fourth capacitors, a chopper switch which switches the polarity of the input terminal and the polarity of the output terminal, to both of which the first capacitor and the second capacitor are connected, a quantizer which compares an added signal and a reference signal to output a digital value, and a digital/analog converter which outputs the feedback analog signal corresponding to the digital value.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.