A communication unit (300, 400, 500) is described that includes at least one antenna (302, 402, 502); a plurality of radio frequency (RF) circuits (304, 310, 404, 410) respectively coupled to at least one antenna (302, 402, 502); at least one sigma-delta modulator (316, 416, 616, 816) comprising a number of stages, each stage comprising at least one signal-feedforward coefficient (603, 604, 605), a filter and a feedback gain element, the at least one sigma-delta modulator (316, 416, 616, 816) coupled to the plurality of RF circuits (304, 310, 404, 410) and configured to perform sigma-delta modulation; and a controller (340, 440, 640, 840) operably coupled to the at least one sigma-delta modulator (316, 416, 616, 816). The at least one sigma-delta modulator (316, 416, 616, 816) comprises an input (315, 415, 602, 801, 802, 902) configured to receive multiple multi-phase input signals and the controller (340, 440, 640, 840) is configured to adjust the at least one signal-feedforward coefficient (603, 604, 605) of the at least one sigma-delta modulator (316, 416, 616, 816) when combining the multiple multi-phase input signals.

A delta-sigma modulator and a delta-sigma converter include an analog amplifying unit to amplify an analog signal and having at least a primary feedback coefficient, a quantizer to quantize an output signal of the analog amplifying unit, a DA converter to perform DA conversion on output of the quantizer and output a feedback signal, an adder-subtractor to input into the analog amplifying unit an analog signal obtained by subtracting the feedback signal from an analog signal input therein, a reset circuit to reset the analog amplifying unit at predetermined periods, and a control circuit to control the analog amplifying unit so that the analog amplifying unit operates as an integrator with the primary feedback coefficient of 1 until a predetermined period elapses after the reset circuit resets the analog amplifying unit and as an amplifier with the primary feedback coefficient of greater than one after the predetermined period has elapsed.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

Proposed is a sigma-delta modulator circuit. The circuit comprises a loopfilter having at least one integrator or resonator section; and a feed-forward path adapted to provide a feed-forward signal to the output of the at least one integrator or resonator section via a filter.

An A/D converter includes an analog input terminal, a successive approximation A/D converter connected to the analog input terminal, the successive approximation A/D converter for generating an upper conversion result at an upper conversion result terminal, the successive approximation A/D converter having an internal D/A converter generating an internal reference voltage at an internal reference voltage terminal, and a delta-sigma A/D converter connected to the analog input terminal and the internal reference voltage terminal, the delta-sigma A/D converter for generating a lower conversion result at a lower conversion result terminal.

A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.

A class-D amplifier includes measurement of speaker current via the low-side drive transistors of the amplifier. In one embodiment, a class-D amplifier includes two high-side transistors, two low-side transistors, a first sense resistor, a second sense resistor, and a sigma delta analog to digital converter ( ADC). The two high-side transistors and two low-side transistors are connected as a bridge to drive a bridge tied speaker. The first sense resistor is connected between a first of the low-side transistors and a low-side reference voltage. The second sense resistor is connected between a second of the low-side transistors and the low-side reference voltage. The ADC is coupled to the bridge to measure voltage across the first sense resistor and the second sense resistor.

A modulator includes a first integrator which has first and second capacitors and integrates an analog input signal and a feedback analog signal, a second integrator which has third and fourth capacitors and integrates an output signal of the first integrator, a differential amplifier which has input and output terminals switched and connected via a switch circuit to either the first and second capacitors or the third and fourth capacitors, a chopper switch which switches the polarity of the input terminal and the polarity of the output terminal, to both of which the first capacitor and the second capacitor are connected, a quantizer which compares an added signal and a reference signal to output a digital value, and a digital/analog converter which outputs the feedback analog signal corresponding to the digital value.

The present disclosure provides a converting module formed in a first die. The first die is coupled to a bus having a bus bit width. The converting module includes an analog-to-digital converter, configured to generate a first digital signal having a first bit width different from the bus bit width; and a sigma-delta modulator, coupled to the analog-to-digital converter, and configured to generate a second digital signal according to the first digital signal. The second digital signal has a bit width equal to the bus bit width. The sigma-delta modulator includes a filter and a quantizer. The number of bits outputted by the quantizer is equal to the bus bit width.

A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.