A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

A delta-sigma modulator includes a first amplifier having an input, a feedback control input, and an output. The input is a first input of the delta-sigma modulator. The delta-sigma modulator further includes a first integrator and a first quantizer. The first integrator has an input and an output. The output of the first amplifier is coupled to the input of the first integrator. The first quantizer has an input and an output. The output of the first quantizer is coupled to the feedback control input of the first amplifier.

A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC comprises or is operably coupled to, a calibration circuit (650, 840) coupled to an input and an output of the at least one pair of comparator latches (336, 356) and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches (336, 356) in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

A sensor signal processing circuit including a delta-sigma analog-to-digital converter (ADC) and a control circuit is disclosed. The circuit is configured to adaptively activate one or more segments of current elements for sequential sampling periods based on a digital signal input to a DAC, wherein less than N current elements are allocated to each segment, each current element in an active segment is enabled and either contributes to a feedback signal of the DAC or does not contribute to the feedback signal, and current elements not in an active segment are disabled. The circuit can be integrated with an acoustic or other sensor as part of a sensor assembly.

A quad signal generator circuit generates four 2.sup.N−1 bit control signals in response to a sampling clock and a 2.sup.N−1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N−1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2.sup.N−1 bit control signals. Outputs of the 2.sup.N−1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all logic states of bits of the four 2.sup.N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N−1 bit thermometer coded signal.

A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

A delta sigma modulator includes two adders, an integrator stage, a reconfigurable local resonator, an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC). A first adder receives an analog input signal at an additive input, and the integrator stage receives an output from the first adder and generates an integrated signal. The reconfigurable local resonator receives the integrated signal and generates a resonator output signal. A second adder receives the resonator output signal, the integrated signal, and the input signal. The ADC receives an output from the second adder and generates a digital output signal which can be provided to other circuits. The DAC receives the digital output signal, and generates and provides a feedback signal to a subtractive input of the first adder. The reconfigurable local resonator acts as a resonator, but reconfigures to act as a low pass filter in response to overload conditions.

A delta sigma modulator includes two adders, an integrator stage, a reconfigurable local resonator, an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC). A first adder receives an analog input signal at an additive input, and the integrator stage receives an output from the first adder and generates an integrated signal. The reconfigurable local resonator receives the integrated signal and generates a resonator output signal. A second adder receives the resonator output signal, the integrated signal, and the input signal. The ADC receives an output from the second adder and generates a digital output signal which can be provided to other circuits. The DAC receives the digital output signal, and generates and provides a feedback signal to a subtractive input of the first adder. The reconfigurable local resonator acts as a resonator, but reconfigures to act as a low pass filter in response to overload conditions.

A quad signal generator circuit generates four 2.sup.N−1 bit control signals in response to a sampling clock and a 2.sup.N−1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N−1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2.sup.N−1 bit control signals. Outputs of the 2.sup.N−1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all logic states of bits of the four 2.sup.N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N−1 bit thermometer coded signal.