Systems and methods include a circuit having a plurality of integrator circuits arranged in series and configured to receive an input signal at a first of the plurality of integrators and generate an output signal at a last of the plurality of integrators, a filter arranged to receive a feedback signal comprising the output signal and generate a filtered feedback signal, which is applied to the input signal before input to the first of the plurality of integrators, and a feedback signal path configured to receive the feedback signal and apply the feedback signal to an input of a second of the plurality of integrators. The circuit may include a class-D amplifier and/or a delta-sigma modulator. The input signal may include an analog audio signal that is amplifier to drive an audio speaker.

A delta-sigma modulator is provided. The delta-sigma modulator includes a multiplexer, a modulation circuit and a demultiplexer. The multiplexer is configured to receive a first analog signal and a second analog signal, and output an input signal. The first analog signal and the second analog signal are in different electrical forms, and the multiplexer is configured to select, in a time-division manner, the first analog signal or the second analog signal as the input signal SIN to be output. The modulation circuit is configured to modulate the input signal into a digital signal. The demultiplexer has a first output terminal and a second output terminal, and selects the first output terminal or the second output terminal in a time-division manner to output the digital signal.

A feedback control system configured to drive a load is disclosed. The feedback control system includes an up-sampling circuit, configured to perform an un-sampling operation on a source signal and produce an up-sampled signal with an up-sampling frequency according to the up-sampled signal and a feedback signal from the load; a delta circuit, coupled to the up-sampling circuit and configured to produce a delta signal; a sigma circuit, configured to produce a density modulation signal according to the delta signal; and a driving device, configured to drive the load according to the density modulation signal with the up-sampling frequency.

A quad signal generator circuit generates four 2.sup.N-1 bit control signals in response to a 2.sup.N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2.sup.N-1 bit control signals. Outputs of the 2.sup.N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2.sup.N-1 bit thermometer coded signal and a time delay applied to the 2.sup.N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2.sup.N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N-1 bit thermometer coded signal.

In some embodiments, an analog-to-digital converter (ADC) architecture can be implemented to process a signal from a charge output sensor. The ADC architecture can include a summing node for receiving a sensor signal from the charge output sensor, and an output node implemented to provide a digital signal representative of the sensor signal. The ADC architecture can further include a charge amplifier implemented to receive an analog signal from the summing node as an input analog signal and generate an output analog signal with a gain, and an ADC circuit implemented to generate the digital signal based on the output analog signal from the charge amplifier. The ADC architecture can further include a feedback circuit implemented between the output node and the summing node.

Aspects of the technology described herein relate to built-in self-testing (BIST) of circuitry (e.g., a pulser or receive circuitry) and/or transducers in an ultrasound device. A BIST circuit may include a transconductance amplifier coupled between a pulser and receive circuitry, a capacitor network coupled between a pulser and receive circuitry, and/or a current source couplable to the input terminal of receive circuitry to which a transducer is also couplable. The collapse voltages of transducers may be characterized using BIST circuitry, and a bias voltage may be applied to the membranes of the transducers based at least in part on their collapse voltages. The capacitances of transducers may also be measured using BIST circuitry and a notification may be generated based on the sets of measurements.

A photoelectric converter comprising a pixel unit and a processor configured to process a pixel signal output from the pixel unit is provided. The processor comprises a ΔΣ AD converter configured to convert the pixel signal into a digital signal. The ΔΣ AD converter comprises a subtracter to which the pixel signal and a subtraction signal are input, an integrator configured to receive an output from the subtracter, a comparator configured to compare an output from the integrator with a predetermined voltage, a decimation filter configured to generate the digital signal based on an output from the comparator, a delay unit configured to delay an output from the comparator, a buffer configured to buffer an output from the delay unit, and a DA converter configured to convert an output from the buffer into an analog signal to generate the subtraction signal.

In an embodiment a sensor arrangement includes a pressure sensor realized as a capacitive pressure sensor, a capacitance-to-digital converter coupled to the pressure sensor and implemented as a delta-sigma analog-to-digital converter and a reference voltage generator having a control input configured to receive a control signal and an output configured to provide a reference voltage, wherein the output of the reference voltage generator is connected to an input of the capacitance-to-digital converter, wherein the reference voltage generator is configured to set a value of the reference voltage as a function of the control signal, and wherein at least two different values of the reference voltage have the same sign and different amounts.

Systems and methods are provided for architectures for an analog feedback class D modulator that increase the power efficiency of the class D modulator. In particular, systems and methods are provided for an analog feedback class D modulator having a digital feed-forward loop. The digital feed-forward loop allows for removal of signal content from an input to an analog-to-digital converter, such that the ADC processes just noise and/or error. Using the techniques discussed herein, the loop filter is low power as it processes error content but not signal content.

A delta-sigma modulator which receives an input signal. The input signal is combined with a feedback signal and the combined signal is filtered by the delta-sigma modulator. The filtered signal is quantized, wherein the feedback signal is generated on the basis of the quantized signal. The quantized signal is output as an output signal. The input signal and/or the filtered signal and/or the feedback signal are filtered in such a way that at least one frequency in an out-of-band frequency range of the input signal is amplified in order to suppress out-of-band quantization noise at the at least one frequency.