Disclosed are systems, methods, and non-transitory computer-readable media for a variable multiplexer for vehicle communication bus compatibility. A device includes a variable multiplexer that can be electronically configured to a desired pinout configuration to provide compatibility with multiple vehicles. For example, the variable multiplexer may be electronically configured based on a pinout configuration used by the vehicle to connect pins in the device to the corresponding pins on the data link connector that provide the same specified function. The device may therefore use a single standardized cable with vehicles using a variety of pinout configurations.

A communication method and device which can improve error correction performance and power consumption without increasing hardware complexity is disclosed. A communication apparatus includes: a decoder for polar codes, that decodes a codeword in which a frame is partitioned according to a predetermined partitioning rule and each partition includes at least one check bit computed by a predefined checksum equation; a memory that stores a frozen set including frozen bit indices, a non-frozen set including non-frozen bit indices, and a susceptible to error (STE) set including STE indices susceptible to decoding error for each partition; and a controller configured to: compute a check sum of at least one decoded bit for each partition according to the predefined checksum equation; responsive to failure of checksum, initiate a recurrent decoding attempt on the partition; and perform a bit-inversion operation on at least one STE index in each recurrent decoding attempt.

A method of cataloging data integrity is herein disclosed. In certain embodiments, the method includes performing a checksum check. The checksum check is performed by selecting a file that includes a first checksum result, selecting a checksum type, determining a processor L1, L2, and L3 cache size, storing the cache size in a variable, breaking the file into a plurality of chunks based on the variable, generating a checksum result for each chunk, storing each checksum result in the variable, and combining the checksum results to return a second checksum result.

Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The mechanisms address ANN system level safety in situ, as a system level strategy tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts that function to detect and promptly flag and report an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.

According to certain embodiments, a method by a transmitter is provided for adaptively generating precoder bits for a Polar code. The method includes acquiring at least one configuration parameter upon which a total number of precoder bits depends. The at least one configuration parameter comprising at least one of an information block length K,a code block length N, and/or a code rate R=K/N. The total number of precoder bits is determined, and the precoder bits for a code block are generated according to the determined total number of precoder bits. The precoder bits are placed within the code block.

Provided is a method for detecting stored data and device, a storage medium and an electronic device. The method includes: the first check information of first data stored in a memory in the current period is determined; the first check information is compared with second check information to obtain a check result, wherein the second check information is check information of second data stored in the memory in a period prior to the current period; and the correctness of storage of the second data is detected according to the check result.

Some embodiments of the invention provide a forwarding element that can be configured through in-band data-plane messages from a remote controller that is a physically separate machine from the forwarding element. The forwarding element of some embodiments has data plane circuits that include several configurable message-processing stages, several storage queues, and a data-plane configurator. A set of one or more message-processing stages of the data plane are configured (1) to process configuration messages received by the data plane from the remote controller and (2) to store the configuration messages in a set of one or more storage queues. The data-plane configurator receives the configuration messages stored in the set of storage queues and configures one or more of the configurable message-processing stages based on configuration data in the configuration messages.

Techniques related to improving power consumption of an LDPC decoder are described. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node to variable node messages implements a plurality of check node processing mode. Operation in each mode consumes a certain amount of power while providing a certain accuracy. Depending on a reliability of a variable node to check node message received by the check node processing unit, an appropriate check node processing mode is selected and used to generate a corresponding check node to variable node message. The reliability can be estimated for a set of variable node to check node messages based on, for instance, syndrome-related parameters.

Techniques related to improving the decoding performance of codewords, such as LDPC codewords, are described. In an example, the error-correction capability of a decoding layer is improved, where the improvements may include lowering the error floor. To do so, higher order information is used in the decoding. Higher order information refers to, during the decoding of a variable node that is in error, using information that is not limited to the variable node and check nodes connected thereto, but includes information related to variable nodes that are also in error and connected to the variable node via satisfied check nodes and related to unsatisfied check nodes connected to such variable nodes.

According to one general aspect, an apparatus may include a storage element configured to store both data and metadata, wherein each piece of data is associated with and stored with a corresponding piece of metadata. The apparatus may include a controller processor. The controller processor may be configured to, in response to a piece of data being written to the apparatus: generate a piece of metadata that includes a set of parameters to facilitate a at least partial repair of a block information map, and embed the piece of metadata with the corresponding piece of data.