A method for determining a first integrity sum including the following steps: determining a first masked item of data by application of an “exclusive OR” operation between a first item of data and a first data mask; —determining a second item of data by application to the first masked item of data of a first cryptographic function, the second item of data being masked by a second data mask; —determining a second integrity sum associated with the second item of data by application to the second item of data of a checksum function; and determining the first integrity sum by application of an “exclusive OR” operation between the second integrity sum and a third integrity sum associated with the second data mask. A computer program and an electronic entity are also described.

Some embodiments of the invention provide a forwarding element that can be configured through in-band data-plane messages from a remote controller that is a physically separate machine from the forwarding element. The forwarding element of some embodiments has data plane circuits that include several configurable message-processing stages, several storage queues, and a data-plane configurator. A set of one or more message-processing stages of the data plane are configured (1) to process configuration messages received by the data plane from the remote controller and (2) to store the configuration messages in a set of one or more storage queues. The data-plane configurator receives the configuration messages stored in the set of storage queues and configures one or more of the configurable message-processing stages based on configuration data in the configuration messages.

The ability to accurately and efficiently calculate and report communication errors is becoming more important than ever in today's communications environment. More specifically calculating and reporting CRC anomalies in a consistent manner across a plurality of communications connections in a network is crucial to accurate error reporting. Through a normalization technique applied to a CRC computation period (e.g., the PERp value), accurate error identification and reporting for each individual connection can be achieved.

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Techniques are described for improving the decoding latency and throughput of an error correction system that includes a bit flipping (BF) decoder, where the BF decoder uses a bit flipping procedure. In an example, different decoding parameters are determined including any of a decoding number of a decoding iteration, a checksum of a codeword, a degree of a variable node, and a bit flipping threshold defined for the bit flipping procedure. Based on one or more of these decoding parameters, a decision can be generated to skip the bit flipping decoding procedure, thereby decreasing the decoding latency and increasing the decoding throughput. Otherwise, the bit flipping decoding procedure can be performed to compute a bit flipping energy and determine whether particular bits are to be flipped or not. Hence, the overall performance (e.g., bit error rate) is not significantly impacted.

In some aspects, methods and apparatus for wireless communications are configured to generate a packet for wireless communication where the packet includes a mark symbol in a preamble of the packet where the mark symbol includes a signature or stamp field in the mark to provide protocol information that indicates the protocol of the packet, such as an 802.11 EHT packet. In some other aspects, a cyclic redundancy check field in the mark symbol may be manipulated in various ways to indicate the protocol of the packet in lieu of providing the signature or stamp field.

Disclosed are devices, systems and methods for reducing the latency of a quasi-cyclic linear code decoder. An example method includes receiving a noisy codeword, the codeword having been generated from a quasi-cyclic linear code and provided to a communication channel prior to reception by the decoder; computing a syndrome based on the noisy codeword; generating a plurality of memory cell addresses, a first memory cell address being a function of the syndrome and subsequent memory cell addresses being within a predetermined address range of the function of the syndrome; reading, in a parallel manner to reduce the latency of the decoder, a plurality of error patterns from the plurality of memory cell addresses and computing a checksum for each of the plurality of error patterns; and determining, based on the checksum for each of the plurality of error patterns, a candidate version of the transmitted codeword.

Techniques are described for improving the decoding latency and throughput of an error correction system that includes a bit flipping (BF) decoder, where the BF decoder uses a bit flipping procedure. In an example, different decoding parameters are determined including any of a decoding number of a decoding iteration, a checksum of a codeword, a degree of a variable node, and a bit flipping threshold defined for the bit flipping procedure. Based on one or more of these decoding parameters, a decision can be generated to skip the bit flipping decoding procedure, thereby decreasing the decoding latency and increasing the decoding throughput. Otherwise, the bit flipping decoding procedure can be performed to compute a bit flipping energy and determine whether particular bits are to be flipped or not. Hence, the overall performance (e.g., bit error rate) is not significantly impacted.

System and method for identifying data corruption in a data transfer over an error-proof communication link, wherein additional structure checksums are formed to secure a data structure during transfer of the data structure, where representatives are associated with the data types, and the structure checksum is formed via the representatives to provide identification of data corruption in a data transfer over an error-proof communication link between a first automation component and a second automation component in industrial control engineering.

Memory controllers bit-flipping (BF) decoders and methods that selectively apply a checksum-aided error reduction (CA-ER) scheme to BF decoding of a low-density parity-check (LDPC) code. In decoding a codeword, a hard decision value resulting from decoding a select variable node is changed when a first condition is satisfied to yield an updated hard decision value. Also, when the first condition is satisfied, a current checksum value after processing the select variable node is updated using the updated hard decision value. The CA-ER scheme is applied when the updated checksum value is not reduced to a set minimum and a second condition based on a previous checksum value, calculated after a previous variable node is processed, is satisfied.