Disclosed herein is an encoder for encoding digital data, said encoder comprising one or more component encoders, one or more interconnections between component encoders, one or more inputs and one or more outputs. The encoder is configured to carry out the following steps:—combining internal input bits received via an interconnection and external input bits received via a corresponding input, to assemble a local information word,—encoding the local information word such as to generate a local code word,—outputting a reduced local code word and handing the same reduced local code word over to said interconnect for forwarding said same reduced local code word via said interconnect to another component encoder or to itself, wherein said encoder is configured to forward on each interconnect the bits of the reduced local code in parallel but with delays that are mutually different for at least a subset of the reduced local code word bits.

The present disclosure relates to a 5G or pre-5G communication system to be provided to support a data transmission rate higher than that of a 4-G communication system, such as LTE, and subsequent communication systems. An apparatus according to one embodiment of the present invention can comprise: a first grouping unit for performing repeated decoding by using an outer decoder and an inner decoder, and grouping, in correspondence to a decoding order, a bit stream, which is received from the outer decoder, from a receiver of a system using binary irregular repeat partial accumulate codes to the inner decoder device; an LLR symbol selection unit for calculating indices of grouped bits having the maximum probability value among the grouped bits, and selecting and outputting a predetermined number of grouped bit LLR values by using the indices of the grouped bits having the maximum probability value; an LLR symbol conversion unit for converting the grouped bit LLR values outputted from the LLR symbol selection unit into symbol LLR values, and outputting the same; a Bahl-Cocke-Jelinek-Raviv (BCJR) processing unit for performing a BCJR algorithm operation on the symbol LLR values; a bit LLR calculation unit for converting an output of the BCJR processing unit into bit LLR values; and a second bit grouping unit for grouping the bit LLR values by predetermined bit units.

Methods and devices are disclosed for receiving and detecting sparse data sequences using a message passing algorithm (MPA) with early propagation of belief messages. Such data sequences may be used in wireless communications systems supporting multiple access, such as sparse code multiple access (SCMA) systems. The determination and passing of one or more messages for an edge between a function node and a variable node in a factor graph representation of the system may be performed in serial with determined values available early for subsequent computations. The serial computations may be scheduled based on various factors.

A decoder performs: computing (S501) a value (i,j) of a performance-improvement metric for each kernel K.sub.i,j; and sorting (S502) the kernels in a list in decreasing order of the values (i,j). The decoder then performs a beliefs propagation iterative process as follows: updating (S503) output beliefs for the W top kernels of the list , and propagating said output beliefs as input beliefs of the neighbour kernels of said W top kernels; updating (S504) output beliefs for each neighbour kernel of said W top kernels following update of their input beliefs, and re-computing (S505) the performance-improvement metric value (i,j) for each said neighbour kernel; setting (S505) the performance-improvement metric for said W top kernels to a null value; and re-ordering (S506) the kernels in the list . Then, the decoder repeats the beliefs propagation iterative process until a stop condition is met.

A method of decoding polar codes based on belief propagation includes conventional belief propagation to decode the polar codes first; when a number of iterations exceeds a predefined upper limit and a cyclic redundancy check fails, the method selects log-likelihood ratio vectors of a plurality of R or L messages from a plurality of log-likelihood ratio vectors generated in each of the iterations and generates another set of log-likelihood ratio vectors (referred to as candidate vector group) to be used as initial values of the R or L messages for a subsequent belief propagation to perform belief propagation decoding iterations and cyclic redundancy check again. Whenever a decoding result passes the cyclic redundancy check, the method exits; otherwise, the method iterates the above procedure until a maximum number of candidate vector groups has been reached.

Systems and methods are described for low power error correction coding (ECC) for embedded universal flash storage (eUFS) are described. The systems and methods may include identifying a first element of an algebraic field; generating a plurality of lookup tables for multiplying the first element; multiplying the first element by a plurality of additional elements of the algebraic field, wherein the multiplication for each of the additional elements is performed using an element from each of the lookup tables; and encoding information according to an ECC scheme based on the multiplication.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Provided herein may be an electronic device using an artificial neural network. The electronic device may include a training data generator configured to determine an input vector corresponding to a trapping set, detected during error correction decoding corresponding to a codeword, and a target vector corresponding to the input vector, and a training component configured to train an artificial neural network based on supervised learning by inputting the input vector to an input layer of the artificial neural network and by inputting the target vector to an output layer of the artificial neural network.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

A polar code may be initially divided into multiple polar component codes where the features of these component codes, such as the number of component codes and the size of the component codes, are determined based on parameters such as the number of available timing units within a transmission interval, interleaving depth, and decoder capability. For each selected component code, the order of code bit generation and their indexes may be determined. The determined indexes may be assigned into different, unique groups according to the order of code bit generation. An interleaving operation may be configured and then executed according to the determined index grouping. In the transmission phase, the code bits may be transmitted based on the identified order of the bit generation in the component polar codes, such as the determined index grouping.