A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.

Provided is a quantum error correction code generating method using a graph state. According to the exemplary embodiment of the present invention, a quantum error correction code generating method using a graph state: includes: generating a graph state representing an adjacency relationship between a plurality of qubits including at least one entangled qubit (ebit); generating a first stabilizer generator which corresponds to the graph state and is configured by a plurality of stabilizers for detecting errors of the plurality of qubits; and generating at least one logical Z operator used for a phase flip operation of a codeword, at least one logical X operator used for a bit flip operation of a codeword, and a second stabilizer generator which is a sub set of the first stabilizer generator, based on the first stabilizer generator and the at least one entangled qubit.

Methods, systems, and devices for wireless communications are described. A wireless communication system may support techniques for correlation-based hardware sequences for layered decoding. In some cases, a user equipment (UE) may partition layers of a submatrix associated with a parity check decoding procedure into a first set of layers and a second set of layers. The UE may sort each set of layers into a respective set of layer orders (e.g., a first set of layer orders and a second set of layer orders) based on an associated set of correlation values. The UE may combine the first set of layer orders and the second set of layer orders to obtain a set of combined layer orders and may select a decoding schedule from a set of decoding schedules used for decoding each of the combined layer orders based on respective schedule lengths for the set of decoding schedules.

The present disclosure relates to a method and an apparatus for decoding polar codes and the polar code decoding method according to an exemplary embodiment of the present disclosure is a polar code decoding method performed by a polar code decoding apparatus which includes receiving a code word vector generated by polar encoding; and decoding the code word vector based on a soft cancellation (SCAN) decoding method and a round-trip belief propagation (BP) decoding method, in the decoding, an inner code of the code word vector may be decoded by the round-trip belief propagation method and an outer code may be decoded by the SCAN decoding method.

A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.

The invention relates to a soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, the present invention provides a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.

A polar-code based encoder is used to perform a transfer of useful data to a polar-code based decoder via a Binary Discrete-input Memory-less Channel. The Divide and Conquer structure consists of a multiplexer having useful data bits and a set of frozen bits as inputs followed by a polarization block of size N=2.sup.L, wherein the polarization block of size N comprises a set of front kernels followed by a shuffler and two complementary polarization sub-blocks of size N/2 with a similar structure as the polarization block of size N but with half its size. A dynamically configurable interleaver is present between the shuffler and one and/or the other of the complementary polarization sub-blocks at each recursion of the Divide and Conquer structure. The configuration of the dynamically configurable interleavers is dynamically modified according to changes detected in the Binary Discrete-input Memory-less Channel.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

A polar encoder kernel, a communication unit, an integrated circuit and a method of polar encoding are described. The polar encoder kernal is configured to receive one or more bits from a kernal information block having a kernal block size of N; and output one or more bits from a kernal encoded block having a block size that matches the kernal block size N; wherein the polar encoder kernal comprises a decomposition of a polar code graph having multiple columns that are processed by a reused single datapath, at least one of said multiple columns contains two or more stages and where each column of the multiple columns is further decomposed into one or more polar code sub-graphs and is configured to process encoded bits one polar code sub-graph at a time.