Patent classifications
H03M13/1191
Channel decoding method and channel decoding device
This method and device makes it possible to implement maximum likelihood decoding of a sparse graph code at low computational complexity in the maximum likelihood decoding of the sparse graph code. This is, in the maximum likelihood of decoding of the sparse graph code, a lost data decoding process by a trivial decoding method and a lost data decoding process by a Gauss elimination method are performed repeatedly and alternately.
METHODS AND PROCEDURES FOR POLAR ENCODING AND DECODING WITH LOW LATENCY
A polar code may be initially divided into multiple polar component codes where the features of these component codes, such as the number of component codes and the size of the component codes, are determined based on parameters such as the number of available timing units within a transmission interval, interleaving depth, and decoder capability. For each selected component code, the order of code bit generation and their indexes may be determined. The determined indexes may be assigned into different, unique groups according to the order of code bit generation. An interleaving operation may be configured and then executed according to the determined index grouping. In the transmission phase, the code bits may be transmitted based on the identified order of the bit generation in the component polar codes, such as the determined index grouping.
METHOD FOR GENERATING ENCODED DATA THAT IS ENCODED BASED ON LOW-DENSITY PARITY-CHECK CODES, AND METHOD FOR DECODING THE ENCODED DATA
A method for generating encoded data includes: generating at least one local LDPC matrix and a global LDPC matrix, the global LDPC matrix relating to each of the at least one local LDPC matrix; repeatedly selecting one of the at least one local LDPC matrix as a target local LDPC matrix until a number t of the target local LDPC matrices are selected, where t is a user-defined number that is greater than one; generating a block matrix that includes the target local LDPC matrices; generating a primary LDPC matrix that includes a first primary matrix part relating to the block matrix, and a second primary matrix part relating to the global LDPC matrix; and encoding data based on the primary LDPC matrix.
Decoding method and apparatus in system using sequentially connected binary codes
The present disclosure relates to a 5G or pre-5G communication system to be provided to support a data transmission rate higher than that of a 4-G communication system, such as LTE, and subsequent communication systems. An apparatus according to one embodiment of the present invention can comprise: a first grouping unit for performing repeated decoding by using an outer decoder and an inner decoder, and grouping, in correspondence to a decoding order, a bit stream, which is received from the outer decoder, from a receiver of a system using binary irregular repeat partial accumulate codes to the inner decoder device; an LLR symbol selection unit for calculating indices of grouped bits having the maximum probability value among the grouped bits, and selecting and outputting a predetermined number of grouped bit LLR values by using the indices of the grouped bits having the maximum probability value; an LLR symbol conversion unit for converting the grouped bit LLR values outputted from the LLR symbol selection unit into symbol LLR values, and outputting the same; a Bahl-Cocke-Jelinek-Raviv (BCJR) processing unit for performing a BCJR algorithm operation on the symbol LLR values; a bit LLR calculation unit for converting an output of the BCJR processing unit into bit LLR values; and a second bit grouping unit for grouping the bit LLR values by predetermined bit units.
ACCELERATED ERASURE CODING SYSTEM AND METHOD
An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.
USING PARITY DATA FOR CONCURRENT DATA AUTHENTICATION, CORRECTION, COMPRESSION, AND ENCYPTION
A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.
METHOD AND APPARATUS FOR GENERATING QUANTUM ERROR CORRECTION CODE USING GRAPH STATE
Provided is a quantum error correction code generating method using a graph state. According to the exemplary embodiment of the present invention, a quantum error correction code generating method using a graph state: includes: generating a graph state representing an adjacency relationship between a plurality of qubits including at least one entangled qubit (ebit); generating a first stabilizer generator which corresponds to the graph state and is configured by a plurality of stabilizers for detecting errors of the plurality of qubits; and generating at least one logical Z operator used for a phase flip operation of a codeword, at least one logical X operator used for a bit flip operation of a codeword, and a second stabilizer generator which is a sub set of the first stabilizer generator, based on the first stabilizer generator and the at least one entangled qubit.
Packet encoding and decoding method and apparatus
A method for encoding and decoding information data using a polar code is provided. The method for encoding includes segmenting information data into a plurality of first packets, generating a plurality of second packets corresponding to the plurality of first packets by adding a corresponding packet Cyclic Redundancy Check (CRC) code to each of the plurality of first packets, fragmenting each of the plurality of second packets into a plurality of data blocks, polar code encoding each of the plurality of data blocks included in a corresponding second packet of the plurality of second packets, and generating a plurality of third packets corresponding to the plurality of second packets by concatenating each polar code encoded data block included in the corresponding second packet. The method for decoding includes decoding the third packet to obtain the information data based on the method for encoding.
Method and Decoder for Soft Input Decoding of Generalized Concatenated Codes
The invention relates to a soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, the present invention provides a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.
METHODS AND PROCEDURES FOR CRC AIDED ENCODING AND BP DECODING FOR POLAR CODES
Methods and apparatuses for relaxed polar coding, including cyclic redundancy check (CRC) aided encoding and belief propagation (BP) decoding for relaxed polar codes in wireless communications, are provided. For example, a method comprises determining: 1) a first set of encoding nodes used for creating CRC bits, 2) a first set of polarization branches, each associated with a respective encoding node of the first set of encoding nodes, and 3) a second set of polarization branches, each of the second set of polarization branches is at least one level higher than a respective polarization branch of the first set of polarization branches. The method also comprises performing polar encoding operation(s) for the second set of polarization branches including relaxation, generating a second set of encoding nodes based on the performed polar encoding operation(s) for the second set of polarization branches, and transmitting polar code bits using the generated second set of encoding nodes.