Patent classifications
H03M13/1505
ERROR CORRECTING CODE FOR CORRECTING SINGLE SYMBOL ERRORS AND DETECTING DOUBLE BIT ERRORS
Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of , wherein is equal to raised to the (2.sup.m/41) power, is equal to a raised to the (2.sup.m/2+1) power, and is a primitive element of GF(2.sup.m). In another embodiment, the system receives a (N, N2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.
Cross-datacenter extension of grid encoded data storage systems
Techniques for extending a grid encoded data storage system to additional datacenters are described herein. A grid of shards with a first index and a second index is created and a set of null shards is added to the grid of shards. When a data object is received for storage in the grid of shards, a set of shards with the same first index is selected for the storage location with at least one null shard and one or more other shards. The null shard is enabled for data storage by allocating a storage device for the null shard. The grid is then updated by storing at least a portion of the data object in the set of shards, updating derived shards in the set of shards, and updating derived shards with the same second index as the updated shards.
Two layer quad bit error correction
A memory device includes one or more memory arrays and a quad bit error correction circuit. The quad bit error correction circuit may include a first layer error correction circuit and a second layer error correction circuit. The first layer error correction circuit may be configured to generate a Hamming correction bit vector, and the second layer error correction circuit may be configured to generate a Golay correction bit vector. The Hamming correction bit vector and the Golay correction bit vector may be used to identify up to four correctable bit errors in data to be stored in the one more memory arrays.
TECHNIQUES FOR COMMUNICATING SYNCHRONIZATION SIGNAL BLOCK INDEX IN A PHYSICAL BROADCAST CHANNEL PAYLOAD
A user equipment (UE) receives a first synchronization signal (SS) block including a first codeword and a second SS block including a second codeword. Each codeword is based on a linear encoding of a physical broadcast channel (PBCH) payload. The PBCH payloads include different timing indicators. The SS blocks are received at different times separated by a time increment. The UE determines, based on the time increment, one or more hypotheses of combined decoding metrics for the first codeword and the second codeword, and decodes the first codeword based on each of at least one hypothesis in the one or more hypotheses. The at least one hypothesis includes a correct hypothesis. The UE determines the first codeword based on an error detection procedure such as CRC verification performed when decoding the first codeword based on the correct hypothesis.
Golay sequences for wireless networks
This disclosure describes the generation and implementation of Golay sequences and Golay Sequence Sets (GSSs) for channel estimation in wireless networks. In one embodiment, this disclosure describes an extension of the Golay sequences Ga and Gb defined in various legacy standards to GSSs. In various embodiments, the disclosed GSSs can include a number of Golay complementary pairs (e.g., Ga and Gb). In one embodiment, the disclosed Golay complementary pairs can meet various predetermined design rules and can be used to define enhanced directional multi-gigabit (EDMG) short training field (STF) and/or channel estimation field (CEF) fields for multiple-input and multiple-output (MIMO) transmission.
Modulation system
A modulation system is configured to employ a dynamically reconfigurable M-ary modulation scheme.
Parity protection for data chunks in an object storage system
The present invention relates to a method and system for providing parity protection in an object storage system. The present invention allows for tracking the storage requirements for chunks in a distributed storage cluster when transitioning from replica-based protection to parity or erasure coding-based protection and when transitioning from parity or erasure coding-based protection to replica-based protection.
Enhanced video decoding with application layer forward error correction
Devices and methods for video decoding with application layer forward error correction in a wireless device are generally described herein. In some methods a partial source symbol block is received that includes at least one encoded source symbol representing an original video frame. In such methods, the at least one encoded source symbol is systematic, the source symbol is decoded to recover a video frame, and the video frame is provided to a video decoder that generates a portion of an original video signal from the recovered video frame.
Belief propagation decoding for short algebraic codes with permutations within the code space
A method of processing data received over a channel includes receiving data representing probabilities associated with a plurality of variables and receiving a parity check matrix associated with a factor graph which includes variable nodes and check nodes connected by edges. After each exchange of messages between the variable nodes and check nodes, messages are calculated based on messages received at the variable nodes and permuted messages to be sent from the variable nodes in the next iteration are calculated by applying a permutation to the calculated messages. The permutation is of a set of permutations which map each codeword of the set of codewords onto a different codeword of the set of codewords. Soft values associated to variable nodes can be accumulated over two iterations of the message exchange processing.
PREDICTIVE CONTEXT-BASED DECODER CORRECTION
Disclosed in some examples are methods, systems, and machine-readable mediums for utilizing context information to create decoding feedback information to improve decoder accuracy and/or performance. In some examples, the context information is from layers of a network stack above the layers in which the decoders are present. The context information may be or be based upon information about previously received and decoded data and/or information about the sender to provide decoding feedback information to the decoder that is used either to correct a previous decoding error or to inform the decoder on which of a plurality of decoding choices is more likely to be correct. This may increase decoding performance by decreasing errors and in some examples, reducing the complexity of choices by eliminating certain decoding possibilities and thus increasing decoder efficiency.