An integrated circuit (IC) includes an encoder circuit. The encoder circuit includes an encoding input configured to receive an input message including one or more data symbols. Each data symbol has N bits and N is a positive integer. The encoder circuit includes an encoding unit configured to perform Reed-Solomon encoding to the one or more data symbols to generate one or more coding symbols. The Reed-Solomon encoding uses a Galois field having an order that is less than 2.sup.N. A coded message that includes the one or more data symbols and the one or more coding symbols is provided at an encoding output of the encoder circuit.

Supporting forward error correction decoding of a word received over a noisy channel. The word being a codeword according to a linear block code prior to transmission. The syndrome is computed for the received word using an obtained parity check matrix. It is generated one or more noise sequences to affect bits of the received word that are in one or more bit positions identified through parity check equations of the obtained parity check matrix identified as erroneous parity check equations by the computed syndrome. Candidate codewords are formed for the noise sequences, respectively, each candidate codeword corresponding to the received word with removal of noise according to a respective one of the noise sequences. It is determined if any one of the formed candidate codewords is an actual codeword according to the LBC by computing the syndrome for the candidate codeword using the obtained parity check matrix.

A memory controller may receive memory data to be stored on a memory. A memory controller may receive metadata related to the memory data. The metadata may be selected from a predetermined list of metadata. A memory controller may identify an encoding polynomial of a plurality of polynomials that is associated with the metadata, each polynomial of the plurality of polynomials associated with different metadata from the predetermined list of metadata. A memory controller may generate a codeword using the encoding polynomial of the plurality of polynomials and the memory data.

An error correction circuit includes a syndrome calculator suitable for generating syndromes from an n-bit codeword for a single unit of time, an error location polynomial calculator suitable for generating error location polynomial coefficients based on the syndromes provided for the single unit of time, an error location calculator suitable for calculating error locations based on the error location polynomial coefficients for the single unit of time, and an error corrector suitable for correcting errors of the codeword based on the error locations for the single unit of time. The error correction circuit operates in a pipelining manner.

Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

To reduce the processing amount of a field multiplication. a denotes a k-th order vector whose elements are a.sub.0, . . . , a.sub.k1 (a.sub.0, . . . , a.sub.k1GF(x.sup.q)). A denotes an n-by-k matrix formed by vertically connecting a identity matrix and a Vandermonde matrix. b denotes an n-th order vector obtained by multiplying the vector a and the matrix A whose elements are b.sub.0, . . . , b.sub.n1 (b.sub.0, . . . , b.sub.n1GF(x.sup.q)). A vector conversion part 11 generates a -th order vector b using elements b.sub.p0, . . . , b.sub.p1 of the vector b. An inverse matrix generation part 12 generates a -by- inverse matrix A.sup.1. A plaintext computation part 13 computes elements a.sub.e0, . . . , a.sub.e1 of the vector a by multiplying the vector b and the inverse matrix A.sup.1.

A method begins by sending a set of read requests to a first set of storage units of the DSN. The method continues by sending a set of read foreign requests to a second set of storage units of the DSN. The method continues by receiving favorable responses to the set of read requests. When a favorable response is received regarding the read foreign request, the method continues by determining whether an encoded data slice (EDS) contained in the favorable response is needed to obtain a decode threshold number of EDSs. When the EDS is needed, the method continues by including the EDSs contained in the favorable response regarding the read foreign request with other EDSs received in the favorable responses to the set of read requests to produce the decode threshold number of EDSs. The method continues by decoding the threshold number of EDSs to recover the data segment.

An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S.sub.1, S.sub.2, and S.sub.3. The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.

A memory device that checks an error of a memory cell and a memory module including the same are disclosed. The memory module includes a first memory device and a second memory device. The first memory device includes a first area in which normal data are stored, and a second area in which error check data are stored. The second memory device stores reliability information about the normal data that is stored in the first area of the first memory device. The first memory device outputs a result of comparing the normal data read from the first area of the first memory device to the error check data read from the second area of the first memory device.

A computer-based distributed error correction scheme with an efficient decoding algorithm is disclosed. The efficiency of the corresponding decoding algorithm, based on standard single source Reed-Solomon error correcting codes, makes the practical employment of the DECC feasible. Various implementation examples are also provided.