The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

Devices, systems and methods for improving the convergence of a bit-flipping decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, computing a plurality of flipping energies for each column of a first subset of columns from the plurality of columns of circulant matrices, computing, based on the plurality of flipping energies, one or more metrics, selecting, based on the one or more metrics, a second subset of columns from the first subset of columns in an order that is different from a sequential indexing order of the second subset of columns, determining, based on processing the second subset of columns using a vertically shuffled scheduling operation, a candidate version of the transmitted codeword.

The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may further compute parity check symbols by solving a system of linear equations that includes the partial syndrome vector and a second matrix. As an example, the second matrix may be decomposed into a lower triangular matrix and an upper triangular matrix, and the parity check symbols may be computed by performing a forward substitution and a backward substitution using the lower and upper triangular matrices. The Reed-Solomon encoder circuit may generate a Reed-Solomon code word by combining the data symbols and the parity check symbols, and provide the Reed-Solomon code word at an output port.

A memory controller system includes error correction circuitry and erasure decoder circuitry. A retry flow is triggered when the memory controller's error checking and correction (ECC) detects an uncorrectable codeword. Error correction circuitry generates erasure codewords from the codeword with uncorrectable errors. The memory controller computes the syndrome weight of the erasure codewords. For example, the erasure decoder circuitry receives the erasure codewords and computes the syndrome weights. Error correction circuitry orders the erasure codewords based on their corresponding syndrome weights. Then error correction circuitry selects a subset of the codewords, and sends them to erasure decoder circuitry. Erasure decoder circuitry receives the selected codewords and decodes them.

The present invention is directed to data communication systems and methods thereof According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

A memory system includes a memory controller. The memory controller executes first calculation of obtaining a first degree to k-th degree error locator polynomials (1≤k<t) by using a syndrome, determines whether error locations can be calculated by the error locator polynomials up to the k-th degree, obtains an initial value of a parameter to be used for second calculation of obtaining error locator polynomials up to t-th degree when it is determined that the error locations cannot be calculated, executes the second calculation using the initial value, calculates the error locations by using an error locator polynomial determined to be able to calculate the error locations among the first degree to k-th degree error locator polynomials or by using error locator polynomials obtained in the second calculation, and corrects errors in the calculated error locations.

A computer-implemented method includes encoding an array of (p−1)×k symbols of data into a p×(k+r) array. The method includes p is a prime number, r≥1, and k≤p−r. The method also includes each column in the p×(k+r) array has an even parity and each line of slope j for 0≤j≤r−1 in the p×(k+r) array has an even parity. The method includes the lines of slope j taken with a toroidal topology modulo p. A computer program product for encoding an array of (p−1)×k symbols of data into a p×(k+r) array includes a computer readable storage medium having program instructions executable by a computer. The program instructions cause the computer to perform the foregoing method.

An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

Devices, systems and methods for improving the convergence of a bit-flipping decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, computing a plurality of flipping energies for each column of a first subset of columns from the plurality of columns of circulant matrices, computing, based on the plurality of flipping energies, one or more metrics, selecting, based on the one or more metrics, a second subset of columns from the first subset of columns in an order that is different from a sequential indexing order of the second subset of columns, determining, based on processing the second subset of columns using a vertically shuffled scheduling operation, a candidate version of the transmitted codeword.

Methods, systems, and devices for wireless communications are described. The user equipment (UE) may initiate a successive cancellation list (SCL) decoding procedure, and may perform the SCL decoding procedure across various nodes (e.g., for each information bit through a decoding tree). At each node, the UE may determine whether a relationship between a first path metric and a second path metric satisfy a threshold. In some examples, the UE may determine whether multiple thresholds are satisfied. If conditions are satisfied (e.g., the relationship between the two path metrics satisfies a threshold), then the UE may decrease a list size of the SCL decoding.