An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data corresponding to a number of physical paths, a time interleaver to time interleave the encoded service data in each physical path, a frame builder to build at least one signal frame including the time interleaved service data, a modulator to modulate data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter to transmitting the broadcast signals having the modulated data.

A controller includes an interface and circuitry. The interface is coupled to multiple memory cells. The circuitry stores a code word in a group of the memory cells, reads the code word using different thresholds to produce first and second readouts, and checks whether approximating each of first and second numbers of readout errors based on syndrome weights is valid. In response to determining that only the approximation of the second number of errors is valid, the circuitry produces a combined readout by replacing a portion of the bits in the second readout with corresponding bits of the first readout, calculates an enhanced syndrome weight for the combined readout and estimates the first number of errors based on the enhanced syndrome weight. The circuitry improves readout performance from at least the group of the memory cells using at least one of the estimated first and second numbers of errors.

A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

A method of processing a received message includes: receiving a message through a receiving terminal to obtain the received message; for each bit in the received message, determining a bit state of the bit according to a bit value of the bit; selectively changing the bit state of each bit according to at least a weighting vector and a current value of a flipping threshold, wherein the bit state has a plurality of change ranges; selectively flipping the bit according to the bit state; and adjusting the current value of the flipping threshold according to a number of times the bit has been flipped within a period of time, whether when the number of times the bit has been flipped within the period of time exceeds an upper limit, the flipping threshold adjustment unit increases the current value of the flipping threshold.

Disclosed are devices, systems and methods for providing hardware implementations of a quasi-cyclic syndrome decoder. An example method of reducing the complexity of a decoder includes receiving a noisy codeword that is a based on a transmitted codeword generated from a quasi-cyclic linear code; computing a plurality of syndromes based on the noisy codeword; selecting a first syndrome from the plurality of syndromes; generating a memory cell address as a function of the first syndrome; reading, based on the memory cell address, a coset leader corresponding to the first syndrome; and determining, based on the noisy codeword and the coset leader, a candidate version of the transmitted codeword.

A Reed Solomon decoder may include a syndrome calculation (SC) circuit, a key equation solver (KES) circuit, and a Chien search and error evaluation (CSEE) circuit. The SC circuit calculates a syndrome from a codeword. The KES circuit includes a plurality of sub-KES circuit and calculates an error location polynomial and an error evaluation polynomial from the syndrome. The CSEE circuit calculates an error location and an error value from the error location polynomial and the error evaluation polynomial. Each of the plurality of sub-KES circuits, the SC circuit and the CSEE circuit respectively constitute pipeline stages. The Read Solomon decoder may also include a FIFO queue that queues the codeword among a plurality of codewords sequentially received, and an error correction circuit that produces error corrected data using an output from the FIFO queue, the error location, and the error value.

A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.

A method for decoding a cyclic code is disclosed. The method includes: determining a plurality of syndromes for the cyclic code; determining, by a hardware processor, a first coefficient and a second coefficient based on the plurality of syndromes; determining, by the hardware processor, a third coefficient based on the second coefficient; and generating an error-locator polynomial based on the first coefficient, the second coefficient, and the third coefficient.

In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K2.sup.(K1)+1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.