A memory device, an error correction device and an error correction method thereof are provided. The error correction device includes a first error correction decoder and a second error correction decoder. The first error correction decoder performs at least one iteration of a first error correction operation on a data chunk, calculates a counting number of syndrome values equal to a set logic value generated in the at least one iteration of the first error correction operation, and generates a control signal according to the counting number. The second error correction decoder receives the control signal and determines whether to be activated to perform a second error correction operation on the data chunk or not according to the control signal. An error correction ability of the second error correction decoder is higher than an error correction ability of the first error correction decoder.

Syndrome calculation circuitry for a decoder of codewords having a first number of symbols, where the decoder receives a second number of parallel symbols, and where the first number is not evenly divisible by the second number, includes multipliers equal in number to the second number. Each multiplier multiplies a symbol by a coefficient based on a root of a field of the decoder. The multipliers are divided into a number of groups determined as a function of a modulus of the first number and the second number. Adders equal in number to the groups add outputs of multipliers in respective ones of the groups. Accumulation circuitry accumulates outputs of the adders. Output circuitry adds outputs of the adders to an output of the accumulation circuitry to provide a syndrome. Selection circuitry directs outputs of the adders to the accumulation circuitry or the output circuitry, and resets the accumulation circuitry.

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data corresponding to a number of physical paths, a time interleaver to time interleave the encoded service data in each physical path, a frame builder to build at least one signal frame including the time interleaved service data, a modulator to modulate data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter to transmitting the broadcast signals having the modulated data.

Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

An error correction code (ECC) decoder includes a syndrome generator and a burst error corrector. The syndrome generator generates global syndrome data and local syndrome data using input data and a parity check matrix based on a constacyclic code. The burst error corrector corrects a correctable error included in the input data using the global syndrome data and the local syndrome data. The input data includes a plurality of data bits arranged along a first direction and a second direction. The ECC decoder simultaneously corrects a single burst error and a multi-bit error. The single burst error occurs on two or more symbols arranged along the first direction in the input data, and each symbol includes two or more data bits. The multi-bit error randomly occurs on two or more data bits in the input data.

A method to correct a fault in application of a Clifford circuit to a qubit register of a quantum computer comprises: (A) receiving circuit data defining the Clifford circuit; (B) emitting outcome code based on the circuit data, the outcome code including a series of outcome checks each corresponding to an anticipated error syndrome of the application of the Clifford circuit to the qubit register; and (C) emitting space-time quantum code corresponding to the Clifford circuit based on the circuit data and on the outcome code, the space-time quantum code including a series of check operators that support quantum-error correction, thereby enabling fault correction in the application of the Clifford circuit to the qubit register.

A method for sending first data as quantum information in qubits and classical second data over a quantum channel, in particular in quantum information communication systems, includes applying quantum error correction (QECC) encoding to the qubits obtaining quantum information codewords, applying intentional errors with error syndromes representing the second classical data to the quantum information codewords obtaining quantum information codewords with intentional errors applied upon, transmitting from a transmitting side the quantum information codewords with intentional errors applied upon over the quantum channel which outputs received codewords at a receiving side, computing error syndromes from the received codewords, performing a QECC error correction operation on the received codewords by applying a correction operator obtained at least by the computed syndromes to obtain corrected codewords, and outputting the corrected codewords and the computed syndromes.

A memory device, an error correction device and an error correction method thereof are provided. The error correction device includes a first error correction decoder and a second error correction decoder. The first error correction decoder performs at least one iteration of a first error correction operation on a data chunk, calculates a counting number of syndrome values equal to a set logic value generated in the at least one iteration of the first error correction operation, and generates a control signal according to the counting number. The second error correction decoder receives the control signal and determines whether to be activated to perform a second error correction operation on the data chunk or not according to the control signal. An error correction ability of the second error correction decoder is higher than an error correction ability of the first error correction decoder.

A computer-implemented method for decoding syndromes of a quantum error correction code, the syndromes comprising measurement data from a quantum computer, the method comprising: receiving syndrome measurement data comprising a plurality of quantum error correction rounds performed on a plurality of qubits; identifying a plurality of non-overlapping first blocks within the syndrome measurement data, wherein: each first block has: a first central block of quantum error corrections rounds; and a first buffer block of quantum error correction rounds, wherein the first buffer block surrounds the first central block, and each first block is surrounded by an interstitial region of quantum error correction rounds; identifying the location of a first set of errors in the plurality of qubits by decoding each first block to provide respective decoded first central blocks and respective decoded first buffer blocks; outputting the location of the first set of errors contained within each decoded first central block.

In a general aspect, a surface code syndrome measurement is performed on a superconducting quantum processing unit. In some implementations, the superconducting quantum processing unit is caused to apply a quantum error correction code including X-type and Z-type stabilizer check patches. Each of the X-type and Z-type stabilizer check patches includes a stabilizer check qubit device and data qubit devices of the superconducting quantum processing unit. Applying the quantum error correction code includes iteratively twirling the data qubit devices in a stabilizer check patch; and evolving the stabilizer check qubit device in the stabilizer check patch and the data qubit devices in the stabilizer check patch under an interaction Hamiltonian. The interaction Hamiltonian includes a plurality of terms interactions between the stabilizer check qubit device in the stabilizer check patch and a respective one of the data qubit devices in the stabilizer check patch.