Patent classifications
H03M13/159
METHOD FOR CONTROLLING STORAGE DEVICE WITH AID OF ERROR CORRECTION AND ASSOCIATED APPARATUS
A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.
Reconfigurable FEC
The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.
ERROR DETECTION AND CLASSIFICATION AT A HOST DEVICE
Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.
APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS
A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data corresponding to a number of physical paths, a time interleaver to time interleave the encoded service data in each physical path, a frame builder to build at least one signal frame including the time interleaved service data, a modulator to modulate data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter to transmitting the broadcast signals having the modulated data.
REED SOLOMON DECODER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
A Reed Solomon decoder may include a syndrome calculation (SC) circuit configured to calculate a codeword from a syndrome ; a key equation solver (KES) circuit configured to calculate an error location polynomial and an error evaluation polynomial from the syndrome; and a Chien search and error evaluation (CSEE) circuit configured to calculate an error location and an error value from the error location polynomial and the error evaluation polynomial, wherein the KES circuit comprises a plurality of sub-KES circuit and each of the plurality of sub-KES circuit, the SC circuit and the CSEE circuit constitutes pipeline stages respectively.
RS error correction decoding method
A decoding method includes that when encoding at a sending terminal, for a m-order primitive polynomial P(x), a primitive field element in galois field GF(2.sup.m) is represented by ; a lookup table f(.sup.j) for different power exponents of is established, where the value of j is selected from all the integers ranging from 0 to 2m1, with a total number of 2m; a generator polynomial G(x) is expanded to obtain a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ; a remainder polynomial R(x), obtained by dividing code word polynomial Q(x) by the generator polynomial G(x), is a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ; and the coefficients of the generator polynomial G(x) and the remainder polynomial R(x) are both calculated using data found in the lookup table f(.sup.j).
LOW-POWER BLOCK CODE FORWARD ERROR CORRECTION DECODER
A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.
INTEGRATION OF COMPRESSION ALGORITHMS WITH ERROR CORRECTION CODES
Aspects and implementations include systems and techniques that detect and correct failure of data storage and communication operations, including obtaining a first plurality of values, selecting a first plurality of error correction values to generate a first codeword, wherein the first codeword is associated with a plurality of syndrome values that encode a second subset of the first plurality of values, and causing a first processing device or a second processing device to restore the first plurality of values based on the first codeword.
Method and associated decoding circuit for decoding an error correction code
A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.
DECODING METHOD AND RELATED APPARATUS
A method of processing a received message includes: receiving a message through a receiving terminal to obtain the received message; for each bit in the received message, determining a bit state of the bit according to a bit value of the bit; selectively changing the bit state of each bit according to at least a weighting vector and a current value of a flipping threshold, wherein the bit state has a plurality of change ranges; selectively flipping the bit according to the bit state; and adjusting the current value of the flipping threshold according to a number of times the bit has been flipped within a period of time, whether when the number of times the bit has been flipped within the period of time exceeds an upper limit, the flipping threshold adjustment unit increases the current value of the flipping threshold.