An embodiment includes a track and hold amplifier device. A device may include an emitter follower transistor coupled to each of an input and an output. The device may also include a charging node coupled between the output and a voltage supply, wherein the charging node is also coupled to the input via the emitter follower transistor. Further, the device may include a cascode switch coupled to each of the input and the output. The cascode switch may be configured to cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode. The cascode switch may also be configured to cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode. The cascode switch may include a MOS-HBT transistor combination operating in class AB mode.

The present invention provides a signal processing apparatus, an optical line terminal, and a communications system. The signal processing apparatus includes a signal input interface, a signal output interface, a reset signal generation unit, a signal amplification and equalization unit, an enable signal generation unit, and N direct-current offset calibration loop units. The signal input interface is connected to the signal amplification and equalization unit, the signal amplification and equalization unit is connected to the signal output interface and the enable signal generation unit, the enable signal generation unit is connected to the N direct-current offset calibration loop units, the N direct-current offset calibration loop units are connected to the signal amplification and equalization unit, and the reset signal generation unit is connected to the N direct-current offset calibration loop units. The present invention can reduce an LA burst settling time, thereby reducing physical overheads of a link.

A circuit and method in an amplifier circuit for filtering a DC offset in differential input signals and inserting a programmable adjustable crosspoint offset in differential output signals. An amplifier circuit includes a differential amplifier circuit configured to amplify differential input signals into differential output signal. The amplifier circuit further includes a feedback circuit coupled between the differential output signals and the differential input signals. The feedback circuit is configured to generate a programmably adjustable crosspoint offset in the differential output signal and a programmably adjustable cutoff frequency of the feedback circuit. An amplifier method includes amplifying differential input signals into differential output signals, generating a programmably adjustable crosspoint offset in the differential output signal, and generating a programmably adjustable cutoff frequency of a feedback circuit between the differential output signals and the differential input signals.

A circuit structure including: a first amplifier stage having an input, and a second amplifier stage connected to the first amplifier stage. The second amplifier stage has an output. The first amplifier stage and the second amplifier stage carry a signal. A controller is configured to measure and modify at least one operational parameter of the signal. A first offset polarity detector-low pass filter (OPD-LPF) circuit connects the second amplifier stage output to the controller through a first controller input. A second OPD-LPF circuit connects the second amplifier stage to the controller through a second controller input. The controller measures an operational parameter of the signal for offset based on input from the first OPD-LPF circuit and the second OPD-LPF circuit. The controller modifies the operational parameter of the signal to correct signal offset.

A DC-coupled burst-mode optical receiver is described. The optical receiver may include an input node that receives a current, e.g., from an optoelectronic converter (such as a photodiode). Moreover, the optical receiver may include a current amplifier, coupled to the input node, that provides an output current based at least in part on the current, where the current amplifier has a shunt feedback path that reduces a bias sensitivity of the current amplifier and a feed-forward path that reduces a DC bias current of the current amplifier. Furthermore, the optical receiver may include a TIA, electrically coupled to the current amplifier, that converts the output current to an output voltage. Additionally, the optical receiver may include a feedback loop coupling an output of the TIA to an input of the feed-forward path.

A transimpedance amplifier circuit includes a feedback control loop that generates a compensation current at an input of a transimpedance amplifier. The feedback control loop includes a differential integrator with an integration capacitor. A time constant associated with charging the integration capacitor is variable as a function of a pre-charge control signal. During a pre-charge phase, the pre-charge control signal is set to a first value so as to set the time constant associated with charging the integration capacitor to a first time constant value. During an operation phase, the pre-charge control signal is set to a second value so as to increase the time constant associated with charging the integration capacitor to a second time constant value greater than the first time constant value for the pre-charge phase.

A comparator circuit outputs a comparison result obtained by comparing a data signal with a threshold whose magnitude is adjusted based on a first offset value at a timing synchronized with a second clock signal whose phase is adjusted based on a difference in phase between the data signal and a first clock signal and a second offset value. An eye monitor circuit thins comparison results obtained in a clock data recovery (CDR) circuit for individual symbols of the data signal by comparing the data signal with a threshold, selects a comparison result corresponding to a symbol for which the comparison result is obtained by the comparator circuit, determines, by comparing the selected comparison result with the comparison result obtained by the comparator circuit, whether or not an error has occurred due to the first or second offset value, and outputs the number of times the error has occurred.

A comparator circuit outputs a comparison result obtained by comparing a data signal with a threshold whose magnitude is adjusted based on a first offset value at a timing synchronized with a second clock signal whose phase is adjusted based on a difference in phase between the data signal and a first clock signal and a second offset value. An eye monitor circuit thins comparison results obtained in a clock data recovery (CDR) circuit for individual symbols of the data signal by comparing the data signal with a threshold, selects a comparison result corresponding to a symbol for which the comparison result is obtained by the comparator circuit, determines, by comparing the selected comparison result with the comparison result obtained by the comparator circuit, whether or not an error has occurred due to the first or second offset value, and outputs the number of times the error has occurred.

Provided is an optical receiver module which includes a conversion unit which converts an input optical signal to an electrical signal, an amplification unit which amplifies the electrical signal and outputs an amplified signal, a reception unit which directly or indirectly receives the amplified signal, and an offsetting unit which offsets the electrical signal such that a difference between a center of an intensity width of the electrical signal and a center of an intensity range of a signal capable of being received by the reception unit becomes small.

A system may include a recovery circuit that may: receive a first detect signal for a first burst signal and a second detect signal for a second burst signal in a burst mode data path; receive a reference pattern signal from a continuous mode data path; generate a first lock signal locked to the first burst signal or locked to the reference pattern signal, and a second lock signal locked to the second burst signal; and output the reference pattern signal from the recovery circuit during a guard period. The frequency of the recovery circuit may be locked to the frequency of the reference pattern signal during the guard period. The guard period may start based on when the first detect signal de-asserts or when the first lock signal de-asserts. During the guard period, the recovery circuit does not output the first burst signal or the second burst signal.