Patent classifications
H04J3/0658
Robust link synchronization in ethernet networks
A second device receives a first synchronization signal transmitted by a first device for training synchronization between the second device and the first device. The second device then transmits one or more initial synchronization response signals to the first device. The one or more initial synchronization response signals are from among a fixed number of synchronization response signals that the second device is configured to transmit to the first device. After transmission of the one or more initial synchronization response signals, the second device receives a second synchronization signal from the first device. After receiving the second synchronization signal, the second device continues transmission of synchronization response signals to the first device until the fixed number of synchronization response signals are transmitted from the second device to the first device.
Clock topology in an ethernet network
A method establishes an improved clock topology for a computation system, where the computation system is a network of nodes, and where multiple nodes are capable of being a grandmaster clock source. The method includes sequentially selecting each selectable node as an acting grandmaster node, the acting grandmaster node sending announce messages, each node with a determinative communication requirement extracting topology information from the announce messages. The above steps are repeated with another node until each selectable node has been an acting grandmaster. The method then includes selecting the clock source based on the best clock topology for the set of nodes with determinative communication requirements.
SERIAL COMMUNICATION APPARATUS AND SERIAL COMMUNICATION METHOD THAT ARE CAPABLE OF EFFICIENTLY ELIMINATING A TIMING LAG BETWEEN SERIAL DATA TRANSFERRED VIA A PLURALITY OF ROUTES IN SERIAL COMMUNICATION
A serial communication apparatus capable of efficiently eliminating a timing lag between serial data transferred via a plurality of routes in serial communication is provided. The serial communication apparatus transfers serial data transmitted from a transmitting side communication unit disposed on a transmitting side to a receiving side communication unit disposed on a receiving side via a plurality of lanes. The transmitting side communication unit comprises a packet transmitting unit configured to divide transmission data into equal parts according to the number of the lanes, distribute the divided transmission data to each lane as a data main body, and add header information indicating the type of the transmission data to the divided transmission data distributed to each lane. The receiving side communication unit comprises a received packet skew adjusting unit configured to adjust skew of data received in each lane. The received packet skew adjusting unit detects the header information of the data received in each lane, writes the data main body of the received data to a data buffer at a detection timing, and starts data transfer from the data buffer to the outside at a timing when a writing access of the data main body of a predetermined number of cycles is completed in each lane.
NETWORK ENTITY FOR SYNCHRONIZATION OVER A PACKET-BASED FRONTHAUL NETWORK
A method performed by a network entity is provided. The method comprises obtaining information indicating uplink, UL, and downlink, DL, time periods in the packet-based fronthaul network occupied by Time-Division Duplex, TDD, radio transmissions transmitted and/or received by the one or more second fronthaul network units over its radio interface. The method further comprises scheduling packet-based synchronization messages between at least the one or more first fronthaul network units and the one or more second fronthaul network units over the packet-based fronthaul network based on the obtained information. A network entity is also provided, as well as, computer programs and carriers.
System and method for isochronous data transmission in industrial network
A method for isochronous data transmission in industrial network. The industrial network includes first sub-network including first industrial devices and first base station, second sub-network including second industrial devices and first routing means, first wireless device configured to provide a communication between the first industrial devices and the first base station, a network controller coupled to the first base station and to the first routing means, and a reference clock. The method including providing first timing information to the first sub-network and second timing information to the second sub-network, configuring the first wireless device to transfer data from the first industrial devices to the network controller based on the first timing information, receiving the data from the first sub-network and transferring the received data from the network controller to the second industrial devices of the second sub-network via routing means using the second timing information.
Field programmable gate array with external phase-locked loop
The present invention relates to a field programmable gate array system that provides phase control with minimal latency.
TIME SYNCHRONIZATION METHOD, TIME SYNCHRONIZATION SENDING END AND RECEIVING END, AND SYSTEM
A time synchronization method, a time synchronization sender, a time synchronization receiver and a time synchronization system are provided. The method includes: determining whether at least one parameter causing recalculation of a best master clock (BMC) algorithm changes; in a case where it is determined that the parameter changes, sending a 1588 standard-based Announce message; and in a case where it is determined that the parameter does not change, sending a keep-alive message of the Announce message. In the present disclosure, by distinguishing keep-alive messages from protocol messages, the problem that a CPU system is busy due to the processing of Announce messages is solved, thereby realizing the optimization of the 1588 protocol, and reducing the impact on the CPU.
Field programmable gate array with external phase-locked loop
The present invention relates to a field programmable gate array system that provides phase control with minimal latency.
Packet-based and time-multiplexed network-on-chip
An integrated circuit can include a Network-on-Chip (NoC) having a router network with first and second shared physical channels. The NoC includes one or more master bridge circuits (MBCs) coupled to the router network, where each MBC provides a packet-based interface to a master client circuit coupled thereto for initiating transactions over the router network. Each MBC sends and receives data for the transactions over the router network as flits of packets according to a schedule. The NoC includes one or more slave bridge circuits (SBCs) coupled to the router network, where each SBC provides a packet-based interface to a slave client circuit coupled thereto to for responding to the transactions over the router network. Each SBC sends and receives the flits over the router network according to the schedule. The flits sent from different client circuits are interleaved using time-multiplexing on the first and second shared physical channels.
TIME-SENSITIVE NETWORKING TIME SYNCHRONIZATION METHOD AND APPARATUS
This application discloses a TSN time synchronization method and apparatus. One example method includes: a first apparatus receives a first TSN time synchronization message from a second apparatus; the first apparatus determines that the first TSN time synchronization message does not carry a first time, where the first time is a system time of a wireless communication system when the second apparatus receives the first TSN time synchronization message; and the first apparatus locally obtains a bridge residence time, write the bridge residence time into the first TSN time synchronization message, and send the first TSN time synchronization message.