H04J3/0688

Synchronizing update of time of day counters using time stamp exchange over a control plane
11496234 · 2022-11-08 · ·

A control plane, available to all of the line cards in a system, is used to exchange time stamps to align the Time of Day counters in the master line cards. The master line cards are locked to a system clock distributed over the backplane by a timing card. The timing card is locked to timing of a slave line card that is synchronized with the grand master. Each master line card synchronizes updating its Time of Day counter based on a time stamp exchange and a local clock locked to the system clock and without the use of a 1 pulse per second signal.

SYSTEMS AND METHODS FOR SYNCHRONIZING DEVICE CLOCKS

A media system, method, and a computer program product for synchronizing device clocks including a plurality of devices having device clocks, where each device is capable of independently selecting a primary clock device from the plurality of devices to coordinate clock synchronization of the remaining devices, e.g., secondary devices. Each device can utilize the same criteria or set of rules to select the primary clock device from among the plurality of devices after an initial exchange of data during a discovery phase. The selection of the primary clock device can be based on random or arbitrary selection, or based on at least one devices characteristic exchanged within the data obtained during the discovery phase. Once selected, the primary clock device coordinates a clock synchronization sequence with each secondary device until each secondary device clock is synchronized to within a predetermined threshold with the primary clock of the primary clock device.

Audio processing apparatus
09753689 · 2017-09-05 · ·

In an audio processing apparatus configured to supply audio data to a processor configured to process audio data, a plurality of receivers, each configured to receive audio data and a work clock carried with the audio data and to supply the audio data to the processor; a plurality of PLL circuits corresponding to the plurality of receivers, each PLL circuit being configured to generate a clock signal based on a word clock received by the corresponding receiver; and a selector configured to select a clock signal from among a plurality of clock signals generated by the plurality of PLL circuits, and to supply the selected clock signal to the processor, the processor outputting the processed audio data at timing synchronized with the selected clock signal are provided.

Authenticating time sources using attestation-based methods

Systems, methods, and computer-readable media for authenticating time sources using attestation-based techniques include receiving, at a destination device, a time reference signal from a source device, the source and destination devices being network devices. The time reference signal can include a time synchronization signal or a time distribution signal. The destination device can obtain attestation information from one or more fields of the time reference signal and determine whether the source device is authentic and trustworthy based on the attestation information. The destination device can also determine reliability or freshness of the time reference signal based on the attestation information. The time reference signal can be based on a Network Time Protocol (NTP), a Precision Time Protocol (NTP), or other protocol. The attestation information can include Proof of Integrity based a Canary stamp, a hardware fingerprint, a Secure Unique Device Identification (SUDI) of the source device, or an attestation key.

Communication node and communication system for performing clock synchronization
11206625 · 2021-12-21 · ·

A communication system comprises a clock generator configured to generate a plurality of system clock signals used to synchronize components included in each of communication nodes in the communication system based on an external clock signal provided by an external clock source located outside the communication system and a physical layer configured to transmit any one of the generated system clock signals to a small cell communicatively connected to an end communication node of the communication system.

Continuance in quality level of an input timing signal

Continuance in quality level of an input timing signal may be provided. Clock source reference timing information may be receive by a first node from a second node as an input. The first node may be downstream from the second node. Then the first node may receive an event message associated with a future event associated with the second node. The first node may then refrain, for a period of time in response to receiving the event message, from switching the input for clock source reference timing information to a source other than the second node.

METHOD AND APPARATUS FOR SWITCHING CLOCK SOURCES

A method for switching clock sources is provided. In the method, Precision Time Protocol, PTP, packets are monitored using each of PTP ports which connect to a new grandmaster (401). A frequency and a phase for the PTP port are calculated based on the PTP packets (402). In response to a successful check for the frequency and the phase, the PTP port is added to a candidate list (403). A phase calibration and a phase stability check may be introduced prior to the alternate BMCA.

Software-controlled clock synchronization of network devices

A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.

Method and apparatus for sending and receiving clock synchronization packet

This application provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.

System and method for providing security for master clocks

Embodiments describe monitoring network activity and behavior of authorized clocks to identify suspicious activity, and in response, removing a clock for an authorized clock list. In one embodiment, a network monitor detects changes in profiles corresponding to the authorized clocks such as a disconnecting from a port, changing a network location, unexpected changes in the clock signal, changes to the clock ID or MAC address, and the like. If the network monitor deems these changes suspicious, it removes the clock from the authorized clock list. When the current master clock fails, the PTP endpoints select a new master clock only if that clock is included in the authorized clock list. In this manner, the network monitor can constantly update the authorized clock list to ensure it contains only clocks that have not been tampered with or replaced with rogue clocks.