A shared bus time interleaves 1 PPS signal and control and coordination information between a primary timing source and line cards that need to be synchronized using the 1 PPS signals. The shared bus utilizes 1 second frames divided into time slots. The 1 PPS signals are interleaved at predetermined locations in the frame so the delays introduced by interleaving the 1 PPS data in time can be precisely removed. While the bus is not being used for 1 PPS signals, the bus is available to send control and coordination information between the line cards and the primary timing source, avoiding the use of another system and increasing utilization of an available communication path.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

A media system, method, and a computer program product for synchronizing device clocks including a plurality of devices having device clocks, where each device is capable of independently selecting a primary clock device from the plurality of devices to coordinate clock synchronization of the remaining devices, e.g., secondary devices. Each device can utilize the same criteria or set of rules to select the primary clock device from among the plurality of devices after an initial exchange of data during a discovery phase. The selection of the primary clock device can be based on random or arbitrary selection, or based on at least one devices characteristic exchanged within the data obtained during the discovery phase. Once selected, the primary clock device coordinates a clock synchronization sequence with each secondary device until each secondary device clock is synchronized to within a predetermined threshold with the primary clock of the primary clock device.

A shared bus time interleaves 1 PPS signal and control and coordination information between a primary timing source and line cards that need to be synchronized using the 1 PPS signals. The shared bus utilizes 1 second frames divided into time slots. The 1 PPS signals are interleaved at predetermined locations in the frame so the delays introduced by interleaving the 1 PPS data in time can be precisely removed. While the bus is not being used for 1 PPS signals, the bus is available to send control and coordination information between the line cards and the primary timing source, avoiding the use of another system and increasing utilization of an available communication path.

A communication system comprises a clock generator configured to generate a plurality of system clock signals used to synchronize components included in each of communication nodes in the communication system based on an external clock signal provided by an external clock source located outside the communication system and a physical layer configured to transmit any one of the generated system clock signals to a small cell communicatively connected to an end communication node of the communication system.

A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

The invention relates to a method for providing a fault-tolerant global time via a time server in a distributed real-time computer system, wherein the time server comprises four components which are connected to one another via a bi-directional communication channel. At a priori defined periodic, internal synchronization times, each of the four components transmits an internal synchronization message, which is simultaneously transmitted to the other three components, from which each internal computer of a component determines a correction term for the tick counter contained in its component and corrects the reading of the local tick counter by this correction term.

The invention relates to a method for providing a fault-tolerant global time and for the fault-tolerant transport of time-controlled messages in a distributed real-time computer system which comprises external computers and a fault-tolerant message distribution unit, FTMDU. The FTMDU comprises at least four components which supply the global time to the external computers by means of periodic external synchronization messages, wherein the external computers each set their local clock to the received global time, wherein each external sender of a time-controlled message transmits two message copies of the message to be sent via two different communication channels to two different components of the FTMDU at periodic sending times defined a priori in timetables, wherein these two message copies are delivered within the FTMDU via two independent communication paths to those two components of the FTMDU which are connected to an external receiver of the message via communication channels.

A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref1) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.

A data processing unit includes a processing circuit that is configured to process data based on a value of a first parameter, a first operator that is selectively set to one of a first state and a second state that are physically identified, a second operator that is set to a physical state indicating the value of the first parameter, and a processor that is configured to set the value of the first parameter indicated by the physical state of the second operator in the processing circuit in a case where the first operator is in the first state at a time of activating the data processing unit, and set a value of the first parameter supplied from the information processing device in the processing circuit in a case where the first operator is in the second state at the time of activating the data processing unit.