In various embodiments, a method is provided. In this method, a first signal is received from a master node, and is sampled to obtain a first sample. The first sample is then quantized to obtain a quantized form of the first sample. A first synchronization sequence is detected from the quantized form of the first sample at T2. First information is received from the master node and the first information is used to indicate a moment T1 at which the master node sends the first synchronization sequence. A second synchronization sequence is sent to the master node at T3. Second information received from the master node and the second information is used to indicate a moment T4 at which the master node detects a quantized form of the second synchronization sequence. Time synchronization is performed based on T1, T2, T3, and T4.

This disclosure provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

This application provides a communication method and an optical module. The method includes: A first optical module determines a first delay. The first optical module sends the first delay to an interface chip. According to the communication method and the optical module that are provided in this application, a delay in the optical module can be reported to the interface chip, so as to improve precision of time synchronization between a master clock and a slave clock, thereby further improving clock precision of a network device.

Systems and methods are provided that include an access point receiving a request from a device to join a first network defined by a first protocol, the access point allocating a slot of a superframe to the device, and the access point allocating remaining slots of the superframe to communication by the access point on a second network defined by a second protocol. Additionally or alternatively, some methods can include the access point enabling a first transceiver communicating via the first protocol and either, when the first transceiver receives first data from the device via the first protocol within a predetermined time of a beginning of the slot, receiving second data from the device via the first protocol for a remainder of the slot or, when the first transceiver module fails to receive the first data, the access point enabling a second transceiver for the remainder of the slot.

Systems and methods for timing over a Metro Transport Networking (MTN) path include detecting a specific block in a stream of blocks, wherein each block is encoded based on a line code, and sampling an output of a clock to determine a timestamp reference based on detection of the specific block, and transmitting timing information based on the timestamp reference. The specific block can be a control block. The timing information can be transmitted via a Precision Time Protocol (PTP) message. The timing information can be transmitted via a plurality of subsequent specific blocks.

A digital routing unit (DRU) within a wireless distribution system (WDS) couples to multiple signal sources (e.g., base band units (BBU)) through common public radio interface (CPRI) links in such a fashion that clock reconditioning circuitry within the DRU is consolidated. That is, instead of each receiver circuit at each input at the DRU having its own clock reconditioning circuit, signals from the same network operator may be multiplexed so as to select a single signal and, from that single signal, recover a cleaned clock signal for use by all the receivers that receive signals from that network operator.

In various embodiments, a method is provided. In this method, a first signal is received from a master node, and is sampled to obtain a first sample. The first sample is then quantized to obtain a quantized form of the first sample. A first synchronization sequence is detected from the quantized form of the first sample at T2. First information is received from the master node and the first information is used to indicate a moment T1 at which the master node sends the first synchronization sequence. A second synchronization sequence is sent to the master node at T3. Second information received from the master node and the second information is used to indicate a moment T4 at which the master node detects a quantized form of the second synchronization sequence. Time synchronization is performed based on T1, T2, T3, and T4.

This application provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.

A cross connect apparatus or system with transparent clocking, consistent with embodiments described herein, connects a selected source or ingress port to a selected destination or egress port and clocks data out of the selected egress port using a synthesized clock that is adjusted to match a recovered clock from the selected ingress port. A transparent clocking system may generate the synthesized clock signal with adjustments in response to a parts per million (PPM) rate detected for the associated recovered clock signal provided by the selected ingress port. The cross connect system with transparent clocking may be a 400G cross connect system with 10G resolution. The cross connect system with transparent clocking may be used in optical transport network (OTN) applications, for example, to provide an aggregator and/or an add-drop multiplexer (ADM) or to provide a reconfigurable optical add-drop multiplexer (ROADM) upgrade to a higher data rate.