A digital routing unit (DRU) within a wireless distribution system (WDS) couples to multiple signal sources (e.g., base band units (BBU)) through common public radio interface (CPRI) links in such a fashion that clock reconditioning circuitry within the DRU is consolidated. That is, instead of each receiver circuit at each input at the DRU having its own clock reconditioning circuit, signals from the same network operator may be multiplexed so as to select a single signal and, from that single signal, recover a cleaned clock signal for use by all the receivers that receive signals from that network operator.

A cross connect apparatus or system with transparent clocking, consistent with embodiments described herein, connects a selected source or ingress port to a selected destination or egress port and clocks data out of the selected egress port using a synthesized clock that is adjusted to match a recovered clock from the selected ingress port. A transparent clocking system may generate the synthesized clock signal with adjustments in response to a parts per million (PPM) rate detected for the associated recovered clock signal provided by the selected ingress port. The cross connect system with transparent clocking may be a 400G cross connect system with 10G resolution. The cross connect system with transparent clocking may be used in optical transport network (OTN) applications, for example, to provide an aggregator and/or an add-drop multiplexer (ADM) or to provide a reconfigurable optical add-drop multiplexer (ROADM) upgrade to a higher data rate.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect OSI model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

Systems and methods are described, and one method includes allocate a continuous duration within a TDMA scheme, for asynchronous NOMA transmissions, and extending from an allocation start time to an allocation termination time, formed of contiguous time slots of the TDMA scheme, and included providing to asynchronous NOMA user terminals an indication of the allocation start time and termination time, indicating allowance to perform asynchronous NOMA transmissions within a start time constraint that starts of the asynchronous NOMA transmissions do not precede the allocation start time, and terminations of the asynchronous NOMA transmissions do not succeed the allocation termination time.

Systems and methods for timing over a Metro Transport Networking (MTN) path include detecting a specific block in a stream of blocks, wherein each block is encoded based on a line code, and sampling an output of a clock to determine a timestamp reference based on detection of the specific block, and transmitting timing information based on the timestamp reference. The specific block can be a control block. The timing information can be transmitted via a Precision Time Protocol (PTP) message. The timing information can be transmitted via a plurality of subsequent specific blocks.

A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect OSI model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

Systems and methods are provided that include an access point receiving a request from a device to join a first network defined by a first protocol, the access point allocating a slot of a superframe to the device, and the access point allocating remaining slots of the superframe to communication by the access point on a second network defined by a second protocol. Additionally or alternatively, some methods can include the access point enabling a first transceiver communicating via the first protocol and either, when the first transceiver receives first data from the device via the first protocol within a predetermined time of a beginning of the slot, receiving second data from the device via the first protocol for a remainder of the slot or, when the first transceiver module fails to receive the first data, the access point enabling a second transceiver for the remainder of the slot.

A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.

A cross connect apparatus or system with transparent clocking, consistent with embodiments described herein, connects a selected source or ingress port to a selected destination or egress port and clocks data out of the selected egress port using a synthesized clock that is adjusted to match a recovered clock from the selected ingress port. A transparent clocking system may generate the synthesized clock signal with adjustments in response to a parts per million (PPM) rate detected for the associated recovered clock signal provided by the selected ingress port. The cross connect system with transparent clocking may be a 400 G cross connect system with 10 G resolution. The cross connect system with transparent clocking may be used in optical transport network (OTN) applications, for example, to provide an aggregator and/or an add-drop multiplexer (ADM) or to provide a reconfigurable optical add-drop multiplexer (ROADM) upgrade to a higher data rate.