A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.

A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.

A method (10) of encapsulating digital communications traffic for transmission on an optical link, the method comprising: a. receiving an input digital communications signal having an input line code (12); b. performing clock and data recovery on the input digital communications signal to obtain input line coded digital communications traffic and a recovered clock signal (14); c. decoding the input digital communications traffic to obtain information bits and non-information bits (16); d. removing the non-information bits (18); e. adding service channel bits for monitoring or maintenance (20); f. assembling the service channel bits and information bits into frames (22); and g. line coding the assembled frames using an output line code to form an encapsulated digital communications signal for transmission on an optical link (24), wherein steps c. to g. are performed using the timing of the recovered clock signal. A communications network receiver configured to implement the method is also provided.

Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect OSI model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect OSI model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

A clock generator for generating a target clock with a frequency equal to the frequency of an input clock divided by a non-integer ratio is disclosed. The clock generator comprises a clock divider. The clock divider is configured to divide the input clock by a first dividing ratio during a first portion of a frame period to generate a first clock slower than the target clock, and divide the input clock by a second dividing ratio during a second portion of the frame period to generate a second clock faster than the target clock. A difference between the first dividing ratio and the second dividing ratio is 0.5 or 1. In some embodiments, the first dividing ratio and the second dividing ration are integers closest to the non-integer ratio.

A method for sending a code block data stream includes adding m first data frames carrying the code block data stream to n physical layer data frames on an Ethernet physical interface. The method includes identifying a location of the first code block of each first data frame in the m first data frames using an alignment marker of a physical layer data frame in the n physical layer data frames. The method includes sending the n physical layer data frames, where m and n are integers greater than or equal to 1.

There is provided a transmission apparatus including: a shift register configured to generate a plurality of timing pulses indicating different timings, from a frame pulse synchronized with a frame signal; and a plurality of signal processors configured to sequentially process the frame signal based on timings indicated by one or more timing pulses among the plurality of timing pulses.

A transmission apparatus including: a first transferer that transfers first data including first identification information; a second transferer that transfers second data including second identification information; a detector that detects the first identification information from the first data transferred from the first transferer; and a storage that stores the second data transferred from the second transferer; wherein the detector detects the second identification information from the second data stored into the storage after detecting the first identification information from the first data.