An optical module for use in an optical system is disclosed, the optical module implementing Precision Time Protocol (PTP) clock functionality therein. The optical module includes an electrical interface with the optical system; circuitry connected to the electrical interface and configured to implement a plurality of functions of functionality; an optical interface connected to the circuitry; and timing circuitry connected to the electrical interface and one or more of the plurality of functions, wherein the timing circuitry is configured to implement the PTP clock functionality.

A control plane, available to all of the line cards in a system, is used to exchange time stamps to align the Time of Day counters in the master line cards. The master line cards are locked to a system clock distributed over the backplane by a timing card. The timing card is locked to timing of a slave line card that is synchronized with the grand master. Each master line card synchronizes updating its Time of Day counter based on a time stamp exchange and a local clock locked to the system clock and without the use of a 1 pulse per second signal.

A method of synchronizing time across a plurality of time domains between a master node and a slave node is provided. The method comprises transmitting, by the master node, a reference time indicated by a hardware clock of the master node to the slave node, synchronizing, by the slave node, a hardware clock of the slave node to the reference time indicated by the hardware clock of the master node, transmitting, by an offset clock layer of the master node, an offset of a first time domain among the plurality of time domains to an offset clock layer of the slave node, and obtaining, by the PTP layer of the slave node, a time in the first time domain by applying the offset of the first time domain to a reference time indicated by the hardware clock of the slave node.

A slave node calculates and stores a propagation delay generated when exchanging a message with a master node. The master node transmits a reference time indicated by a hardware clock of the master node, and the slave node synchronizes a hardware clock of the slave node to the reference time indicated by the hardware clock of the master node. The master node transmits a time value in a first time domain to the slave node, where the time value is calculated by the master node by adding an offset of the first time domain to the reference time. The slave node calculates the offset using the time value and the stored propagation delay, and obtains a time in the first time domain by applying the calculated offset to a reference time indicated by the hardware clock of the slave node.

A multi-chip module (MCM) may include a substrate, and first and second physical-layer (PHY) chips mounted on the substrate. In some implementations, the first PHY chip includes a multiplexer and a PHY circuit. The multiplexer is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into first and second data streams, to output the first data stream to the PHY circuit, and to output the second data stream to the second PHY chip. In some implementations, the first PHY includes a router and a PHY circuit. The router is configured to receive a plurality of data packets from a MAC device, to route one or more of the data packets having a first address to the PHY circuit, and to route one or more of the data packets having a second address to the second PHY chip.

According to one embodiment, there is provided a multiplexing method including: receiving a TS over IP packet from a plurality of encoders which are disposed at physically remote places, or which are disposed in a virtual environment on a cloud computing system where physical locations are unidentifiable; performing multiplexing after compensating for a delay and jitter of a transmission path, based on a timestamp which is stamped on an RTP header of the TS over IP packet; and performing, with respect to a PCR packet, either multiplexing after compensating for the delay and the jitter, based on a time re-generated in a multiplexing apparatus, or multiplexing by generating a PCR packet in the multiplexing apparatus.

A physical layer (PHY) processor of a network device receives: a timing packet that includes initial timing information, and one or more indicators of one or more parameters to be used by the PHY processor for embedding timing information into the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded by the PHY device, ii) an indicator of a location of a field in the timing packet at which the timing information is to be embedded into the timing packet by the PHY device, and iii) an indicator of whether timing information in the timing packet needs to be updated by the PHY device. The PHY processor updates, based on the one or more indicators, the initial timing information in the timing packet.

The present invention disclose a clock synchronization method. By the operations of: receiving a plurality of data packets sent by a host and acquiring receiving time when each data packet is received and a sending interval at which each two adjacent data packets are sent, wherein each data packet comprises a packet sequence and a first packet timestamp when the first data packet is sent; carrying out screening processing on all data packets according to the sending interval and the receiving time and packet sequence of each data packet so as to obtain at least one valid data packet; obtaining a time compensation value according to the receiving time and packet sequence of each valid data packet, the first packet timestamp, and the sending interval; and adjusting time of a slave according to the time compensation value so as to realize clock synchronization between the slave and the host.

A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.