In a general aspect, a network transmission interface can include, within an egress data path, a physical coding sublayer (PCS) operating in a constant bitrate domain for transmitting data frames on a network link; a timestamp unit configured to insert timestamps in payloads of the frames; a transmission media access control (MAC) unit located at a boundary between the constant bitrate domain and a variable bitrate domain, configured to receive the frames at a variable bitrate, encapsulate the frames, and provide the encapsulated frames at a constant bitrate; a MAC layer security unit located downstream from the timestamp unit, configured to sign and optionally encrypt the payloads and expand each frame with a security tag and an integrity check value (ICV). The timestamp unit and the MAC layer security unit (26b) can both operate in the constant bitrate domain.

One embodiment is directed to a technique for in-band signaling of time stamp information where a kernel driver executing in kernel space modifies a received timing message (for example, a Precision Time Protocol (PTP) Delay Request message) to include timing information associated with the time the timing message was received by a network interface. This is done so that an application running in the user space can obtain the timing information from the modified timing message and reconstruct a timestamp for the received timing message (for example, a PTP T4 timestamp) for use in implementing at least a part of a packet-based synchronization protocol (for example, the PTP).

Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.

A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

Techniques for facilitating a robust clock synchronization across a computer network that presumes network jitter exists are discussed herein. A first device and a second device transceive a plurality of sets of time-synchronization messages to synchronize a synchronization clock of the second device to a first clock of the first device. The second device calculates a smoothing of time delay data of a plurality of sets. The time delay data is associated with a transmission duration of time-synchronization messages of the sets of the plurality. The second device sets a synchronization clock based on a time at the first device and the smoothed time delay data.

According to one embodiment, a communication control device includes a transmission control unit and a communication unit. The transmission control unit is configured to control transfer start timing of a first message stored in a queue, based on gate control information. The communication unit is configured to transmit the first message transferred from the transmission control unit in accordance with the transfer start timing. The transfer start timing of the first message is determined based on a transmission cost at a time when a second message, which has been already determined to pass through the gate, is transmitted by the communication unit, and a transfer status of the second message between the transmission control unit and the communication unit.

A network switch can include a precision time protocol (PTP) module and a circuit board. The PTP module can provide a first clock signal and include a predetermined interface. The circuit board can include a socket, an oscillator and a selection unit. The socket can be inserted by the predetermined interface to receive the first clock signal. The oscillator can provide a second clock signal. The selection unit can include a first terminal, a second terminal, an output terminal and a selection terminal. The first terminal can receive the first clock signal when the predetermined interface is inserted into the socket. The second terminal can receive the second clock signal. The output terminal can output one of the first clock signal and the second clock signal. The selection terminal can receive a selection signal to control the output terminal to output the first clock signal or the second clock signal.

In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.

A control plane, available to all of the line cards in a system, is used to exchange time stamps to align the Time of Day counters in the master line cards. The master line cards are locked to a system clock distributed over the backplane by a timing card. The timing card is locked to timing of a slave line card that is synchronized with the grand master. Each master line card synchronizes updating its Time of Day counter based on a time stamp exchange and a local clock locked to the system clock and without the use of a 1 pulse per second signal.

An optical link channel auto-negotiation method and apparatus, a non-transitory computer-readable storage medium are disclosed. The optical link channel auto-negotiation method may include at least one of the following: configuring a receiving rate, determining whether a receive clock recovered from received data by a physical layer (PHY) module is locked, and in response to determining that the receive clock recovered from the received data by the PHY module is locked, determining that the receiving rate is configured correctly; configuring a first predetermined parameter in response to determining that the receiving rate is configured correctly, determining whether code block data of the PHY module is in a synchronized state, and in response to determining that the code block data of the PHY module is in a synchronized state, determining that the first predetermined parameter is configured correctly.