A network device adapted for sending a synchronization packet to a slave device. The synchronization packet includes a timestamp field and a correction field. The network device includes a counting circuit, a communication chip, and a processor. The counting circuit is configured to provide a calendar time TOD. The communication chip includes a first port, a second port, and a timestamp circuit which has a bit number N. The processor is coupled to the first port of the communication chip. The processor is configured to: obtain a remainder R according to the calendar time TOD and the bit number N; and write the calendar time TOD and the remainder R into the synchronization packet.

A timestamp unit and a communication control unit for a user station. The timestamp unit includes a memory, which cyclically stores a timestamp of a message, which is transmitted via a communication network, an address counter, which is incrementable with each storing of a timestamp of a message, so that the value of the address counter corresponds to an address at which the timestamp is stored in the memory, a first interface to a host control unit via which the timestamp of a message is capturable, and a second interface to a communication control unit, which creates or reads at least one message for/from the user station, the interface including a connection for receiving a trigger signal from the communication control unit, which prompts the capturing of a timestamp, and a connection for transmitting a signal to the communication control unit, which includes the value of the address counter.

A line card of a network box receives a SYNC input signal and generates a first time stamp based on receipt of the SYNC input signal. The line card generates a system clock signal in a phase-locked loop and generates a SYNC output signal by dividing the system clock signal in a divider circuit. The SYNC output signal is fed back to an input terminal as a SYNC feedback signal. A time stamp is generated based on receipt of the SYNC feedback signal. The line card determines a time between the SYNC input signal and the SYNC feedback signal based on the first time stamp and the second time stamp. The timing of the SYNC output signal is adjusted based on the time difference using a coarse time adjustment by adjusting a divide ratio of the divider circuit and using a fine time adjustment in the phase-locked loop based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

A small form-factor pluggable (SFP) time signal adapter module includes a printed circuit board, a cable connector mounted to the printed circuit board, and a differential receiver coupled to the cable connector, one or more of the plurality of wire traces, and an SFP edge connector. The printed circuit board has a plurality of wire traces and a plurality of pads of the SFP edge connector is at least coupled to two of the plurality of wire traces. The cable connector is coupled to at least one or more of the plurality of wire traces. The cable connector coupes to a connector of a cable to receive a differential time reference signal. The differential receiver receives and differentiates the differential time input signal to generate a single ended time reference signal that is coupled to a pad of the SFP edge connector.

A user equipment device (UE) comprises physical layer circuitry configured to transmit and receive radio frequency electrical signals with one or more nodes of a radio access network, an audio subsystem configured to generate frames of audio data, and processing circuitry. The processing circuitry is configured to calculate a time delay from generation of an audio data frame by the audio subsystem of the UE device to transmission of an audio data packet by the physical layer circuitry during a voice call, and decrease the time delay to a delay value that preserves a specified minimum time for delivery of the generated audio data frame to the physical layer circuitry to meet a scheduled transmission time of the audio data packet.

Described is a digital interface and related systems, method and devices. In some embodiments, an interface may be an interface between a link layer and a physical transmission medium. The interface may be configured for a bit rate and/or reference clock that limits electromagnetic emissions (EME), for example, as compared to a bit rate and/or clock rate specified by interfaces widely used in industry.

Disclosed is a time synchronization method and apparatus. The method includes: receiving a time synchronization message sent by an upstream device through a clock port; obtaining a message rate parameter in the time synchronization message; according to the message rate parameter, correcting a time synchronization message loss detection parameter of a slave clock port, wherein the time synchronization message loss detection parameter is used to detect whether the time synchronization message is lost; and according to a correction result, keeping clock synchronization with the upstream device.

A packet processing method includes receiving a first packet by a first receiving interface of a media conversion module of a first network device, where the first packet includes a first alignment marker (AM), sending a second packet by a first sending interface of the media conversion module, where the second packet includes the first AM, and the second packet is the first packet processed by the media conversion module, and calculating a time interval T.sub.1 between a time at which the media conversion module receives the first packet and a time at which the media conversion module sends the second packet, where the T.sub.1 is used to compensate for a first timestamp at which the first network device receives or sends the third packet.

The present patent application provides a method, an apparatus, and a system for generating a timestamp. The method includes: receiving, by a data packet processing unit, a data packet sent by a physical layer transceiver unit or an upper layer, and identifying whether the data packet is a precise time synchronization protocol PTP data packet, and if the data packet is a PTP data packet, generating, according to a physical layer delay provided by a physical layer delay acquiring unit and a non-physical layer delay provided by a non-physical layer delay acquiring unit, a precise timestamp and rewriting a timestamp field in the data packet.

Medical devices can perform a plurality of functions, such as sensing, monitoring, deriving and/or calculating various physiological statuses of a patient (e.g., blood pressure, temperature, respiration rate, etc.). Medical devices can also be used to image part or all of a patient's body, to deliver a treatment, or to manage information related to a patient's care. The present disclosure is directed at one or more devices that perform these functions using a plurality of processing circuits, wherein each processing circuit has a timing circuit with a local clock. These processing circuits can be connected via a network, and each timing circuit can communicate with at least one other timing circuit in order to detect and correct time-differences between their local clocks. In this way, multiple processing circuits can be synchronized with each other to facilitate diagnosis or treatment of a patient's condition, or other aspects of a patient's care.