The invention relates to the field of computer engineering and cryptography and, in particular, to methods for implementing linear transformations that operate with a specified speed and require minimum amount of memory, for further usage in devices for cryptographic protection of data. The technical result enables the selection of interrelated parameters (performance and required amount of memory) for a particular computing system when implementing a high-dimensional linear transformation. The use of the present method allows for a reduction of the amount of consumed memory at a given word size of processors employed. To this end, based on a specified linear transformation, a modified linear shift register of Galois-type or Fibonacci-type is generated according to the rules provided in the disclosed method, and the usage thereof enables to obtain the indicated technical result.

A noise generation module generates power consumption noise to conceal the power consumption characteristics of a cryptographic module. The cryptographic module performs first non-linear transformation on received data, and the noise generation module performs second non-linear transformation on received data during the operational period of the first non-linear transformation.

Provided is a method of an electronic device for performing ultra wide band (UWB) communication. The method includes receiving upper bit information including pre-set at least one parameter via a UWB command interface (UCI), obtaining slot count information and key information including a constant key value, and performing static scrambled timestamp sequence (STS) generation, based on the upper bit information, the slot count information, and the key information.

A method includes receiving data and a plurality of values at a processor. The data can include real-valued data and/or complex data. The plurality of values includes one of a plurality of random values or a plurality of pseudo-random values. The method also includes generating an automorphism, via the processor, based on the plurality of values, and partitioning the data, via the processor, into a plurality of data blocks. The automorphism includes at least one of a linear transformation or an antilinear transformation. Each data block from the plurality of data blocks can have a predefined size. The method also includes applying the automorphism, via the processor, to each data block from plurality of data blocks, to produce a plurality of transformed data blocks, and causing transmission of a signal representing the plurality of transformed data blocks.

A system can include: a plurality of processing Cores; a Package Interconnect communicatively coupled with the plurality of processing Cores; a Configurable LFSR PRV Generator Hardware Array means communicatively coupled with the Package Interconnect; a Galois Multiplication Hardware Accelerator means communicatively coupled with the Package Interconnect; an Extended Euclidian Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect; and a Fischer-Yates Shuffle Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect.

Shannon's equivocation, the conditional entropy of key or message with respect to a specific ciphertext, is the primary indicator of the security of any secrecy system, in that when key equivocation H E (K) or message equivocation H E (M) attain log 0 (or 1) under a brute-force attack, the system is compromised and has no security. We propose a simplistic equivocation definition of security which distinguishes between secure/unsolvable and insecure/solvable encipherments. Whilst equivocation may be used practically in a passive manner to cryptanalyse finite-length key insecure/solvable secrecy systems to determine the length of ciphertext required to compromise the secrecy system, the invention in this patent offers a cryptographic design framework which allows for the equivocation of finite-length key systems to be actively engineered using equivocation augmentation, such that the residual key and message equivocation of any cryptosystem may be continuously augmented at a faster rate than it is lost, effectively ensuring that equivocation can never attain log 0. In short, it allows for the encryption of any length of message with any finite length key into a ciphertext with secure/unsolvable security characteristics. Alternatively, it allows for the cryptographic engineering of information theoretic security in all finite length key systems. The invention is primarily aimed at solving two major problems: (a) a viable practical security solution against future quantum computing/artificial intelligence threats (the QC/AI problem), and (b) a viable practical security solution to the privacy/national interest dichotomy problem, in that it allows for the engineering of security systems which are capable of simultaneously supporting both the absolute privacy of individual users and the security interests of the user group at large. Various methods, apparatuses, and systems are described which allow for the implementation of a secure/unsolvable secrecy system which is fast, extensible, simple to implement in hardware and software, and able to be incorporated by or with any existing security solution or cryptographic primitives.

A technique for generating a keystream (128) for ciphering or deciphering a data stream (122) is provided. As to a method aspect of the technique, a nonlinear feedback shift register, NLFSR (112), including n register stages implemented in a Galois configuration is operated. At least one register stage of the implemented n register stages is representable by at least one register stage of a linear feedback shift register, LFSR. A first subset of the implemented n register stages is representable by a second subset of a second NLFSR. A number of register stages receiving a nonlinear feedback in the second NLFSR is greater than one and less than a number of register stages receiving a nonlinear feedback in the implemented NLFSR. The keystream (128) is outputted from a nonlinear output function (118). An input of the nonlinear output function (118) is coupled to at least two of the implemented n register stages of the NLFSR (112).

A computer-implemented method, computer program product, and system are provided. The method includes generating, by a password management system using a set of Hardware Random Number Generators (HRNGs), at least one salt based on statistics of a set of random numbers with given distributions generated by the set of HRNGs. The method further includes forming, by a processor, a hashed password based on the at least one salt.

A method includes receiving data and a plurality of values at a processor. The data can include real-valued data and/or complex data. The plurality of values includes one of a plurality of random values or a plurality of pseudo-random values. The method also includes generating an automorphism, via the processor, based on the plurality of values, and partitioning the data, via the processor, into a plurality of data blocks. The automorphism includes at least one of a linear transformation or an antilinear transformation. Each data block from the plurality of data blocks can have a predefined size. The method also includes applying the automorphism, via the processor, to each data block from plurality of data blocks, to produce a plurality of transformed data blocks, and causing transmission of a signal representing the plurality of transformed data blocks.

A machine instruction is provided that has associated therewith an opcode to identify a perform pseudorandom number operation, and an operand to be used by the machine instruction. The machine instruction is executed, and execution includes obtaining a modifier indicator. Based on the modifier indicator having a first value, performing a deterministic pseudorandom number seed operation, which includes obtaining seed material based on information stored in the second operand. A selected hash technique and the seed material are used to provide one or more seed values, and the one or more seed values are stored in a parameter block.