Multipath filters are provided herein. In certain configurations, a multipath filter includes multiple filter paths or circuit branches that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a double-in double-switched (DIDS) downconverter that downconverts the input signal with two different clock signal phases to generate a downconverted signal. Each filter circuit branch further includes a filter network that generates a filtered signal by filtering the downconverted signal and an upconverter that upconverts the filtered signal to generate a branch output signal. Additionally, the branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

An apparatus includes an FFE circuit, including a clock generator creating multiple sub-rate phases of an input clock, and a multi-phase sampler responsive to a data signal and to the multiple sub-rate phases generated by the clock generator. The sampler is configured to sample the data signal and to generate held sample outputs corresponding to the multiple sub-rate phases. A SC equalization circuit in the FFE circuit has two states and is responsive to inputs from the multi-phase sampler output and the clock generator. The SC equalization circuit is configured to form outputs using the two states. A variable gain output stage in the FFE circuit is responsive to the outputs from the SC equalization circuit and is responsive to gain control signal(s) to provide variable gains to corresponding outputs of the SC equalization circuit to form equalized outputs based on the data signal.

A method of operation for an Ethernet transceiver is disclosed. The method includes receiving, with receiver circuitry from a link partner transceiver, a data signal carrying data. A threshold change in signal quality of the data signal is detected. A fast retrain operation is initiated in response to the threshold change in signal quality. The fast retrain operation includes adaptively self-updating the receiver circuitry based on filter information generated by the receiver circuitry independently of signals received from the link partner transceiver.

Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.

Apparatuses, methods and computer programs are described including receiving a sequence of messages at a correction module of a transmission system, wherein the transmission system includes a transmitter, a channel, the correction module and a receiver, wherein the correction module includes a correction algorithm having at least some trainable weights; converting the received sequence of messages into a converted sequence of messages using the correction algorithm; receiving a reward or loss function from the receiver based on the modified sequence of messages; and training at least some weights of the correction algorithm based on the received reward or loss function.

An apparatus includes an FFE circuit, including a clock generator creating multiple sub-rate phases of an input clock, and a multi-phase sampler responsive to a data signal and to the multiple sub-rate phases generated by the clock generator. The sampler is configured to sample the data signal and to generate held sample outputs corresponding to the multiple sub-rate phases. A SC equalization circuit in the FFE circuit has two states and is responsive to inputs from the multi-phase sampler output and the clock generator. The SC equalization circuit is configured to form outputs using the two states. A variable gain output stage in the FFE circuit is responsive to the outputs from the SC equalization circuit and is responsive to gain control signal(s) to provide variable gains to corresponding outputs of the SC equalization circuit to form equalized outputs based on the data signal.

Increase the effective data rate of high-speed data communication. It has a memory unit, a reception signal line, and a transmission signal line capable of communicating with an external device via a control circuit and an equalizer, controllers for controlling transmission and reception of signals to and from the external device, and a correction coefficient associated with an identification information and the identification information of the external device. The control circuit sets the correction coefficient associated with the identification information to the equalizer.

An ONU comprises a receiver configured to receive a continuous-mode TDMA downstream signal from an OLT; a PD coupled to the receiver and configured to convert the continuous-mode TDMA downstream signal to an electrical signal or an RF signal; an ADC coupled to the PD and configured to convert the electrical signal or the RF signal to a digital signal; and a burst-mode data recovery stage coupled to the ADC and configured to perform data recovery on a segment of the digital signal corresponding to the ONU, the burst-mode data recovery stage comprises a synchronization stage configured to perform synchronization on the segment.

A method of operation for an Ethernet transceiver is disclosed. The method includes entering a fast retrain sequence of steps. The fast retrain sequence of steps includes transferring two-level symbols to a link partner; and directly following transferring of the two-level symbols, transferring multi-level symbols to the link partner, the multi-level symbols having greater than two symbol levels.