A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap position to the descrambler output by-passes logic elements located in the data path from the first tap to the descrambler output, thereby reducing delay in the descrambler circuit after the reconfiguration (i.e., the “lock-shift” operation). The tap position change may be communicated by a mode manager to a corresponding scrambler circuit, for applying a matching reconfiguration in the scrambler circuit, either directly via an I/O line or indirectly. The indirect route includes in-band transmissions between two ICs with two sets of self-synchronizing scrambler/descrambler pairs, and is based on monitored receiver LFSR output signals that indicate when a scrambler/descrambler pair is synchronized or whether the output of a descrambler circuit comprises descrambled data.

A millimeter-wave communication system includes a transmitter and a receiver. The transmitter is configured to be connected to a waveguide that is transmissive at millimeter-wave frequencies, the waveguide having a propagation parameter that varies with frequency at the millimeter-wave frequencies. The transmitter is configured to generate a millimeter-wave signal comprising multiple sub-carriers that are modulated with data, wherein each sub-carrier is modulated with a respective portion of the data and is subjected to only a respective fraction of a variation in the propagation parameter, and to transmit the millimeter-wave signal into a first end of the waveguide. The receiver is configured to receive the millimeter-wave signal from a second end of the waveguide, and to extract the data from the multiple sub-carriers.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap position to the descrambler output by-passes logic elements located in the data path from the first tap to the descrambler output, thereby reducing delay in the descrambler circuit after the reconfiguration (i.e., the “lock-shift” operation). The tap position change may be communicated by a mode manager to a corresponding scrambler circuit, for applying a matching reconfiguration in the scrambler circuit, either directly via an I/O line or indirectly. The indirect route includes in-band transmissions between two ICs with two sets of self-synchronizing scrambler/descrambler pairs, and is based on monitored receiver LFSR output signals that indicate when a scrambler/descrambler pair is synchronized or whether the output of a descrambler circuit comprises descrambled data.

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

A concurrent multi-band linearized transmitter (CMLT) has a concurrent digital multi-band predistortion block (CDMPB) and a concurrent multi-band transmitter (CMT) connected to the CDMPB. The CDMPB can have a plurality of digital baseband signal predistorter blocks (DBSPBs), an analyzing and modeling (A&M) stage, and a signal observation feedback loop. Each DBSPB can have a plurality of inputs, each corresponding to a single frequency band of the multi-band input signal, and its output corresponding to a single frequency band; each output connect corresponding to an input of the CMLT. The A&M stage can have a plurality of outputs connected to and updating the parameters of the DBSPBs, and a plurality of inputs connected to either both outputs of the signal observation loop or the output of the subsampling loop and to outputs of the DBSPBs. The A&M stage can perform signals' time alignment, reconstruction of signals and compute parameters of DBSPBs.

The disclosed systems, structures, and methods are directed to a superposition based transceiver. The configurations presented herein employ a plurality of encoders configured to encode a plurality of input digital data streams, wherein each of the plurality of input digital data streams operates at different data rates, a plurality of modulators configured to modulate the plurality of encoded digital data input streams. In addition, a plurality of transmitter filters configured to perform up-sampling and filtering of the plurality of modulated digital data streams, and a signal mixer configured to combine the plurality of up-sampled and filtered digital data streams into a single aggregate digital data stream in a manner such that the single aggregate digital data stream contains spectral characteristics that substantially conform to both a central area and a skirt area of a unified spectral emission mask, as specified by European Telecommunications Standards Institute (ETSI).

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.