Patent classifications
H04L25/03853
Transmission apparatus and communication system
A transmission apparatus includes a waveform processing circuit. The waveform processing circuit is configured to receive a modulated signal indicating each of values of pulses by one of four signal levels including first, second, third, and fourth signal levels ascending in this order. The waveform processing circuit is configured to output a signal corresponding to the modulated signal. A portion of the output signal corresponding to a portion of the modulated signal that transitions between the first and fourth signal levels, transitions between a first adjusted signal level different from the first signal level and a second adjusted signal level different from the fourth signal level. The transmission apparatus is configured to transmit a signal corresponding to the signal output from the waveform processing circuit through a wired communication path.
SYSTEM WITH MULTIPLE VIRTUAL RADIO UNITS IN A RADIO UNIT THAT IS REMOTE FROM AT LEAST ONE BASEBAND CONTROLLER
A communication system is provided. The communication system includes a at least one baseband controller configured to process signals in a baseband frequency band. The communication system also includes at least one radio unit that is physically remote from the at least one baseband controller. Each radio unit includes a plurality of virtual radio units (VRUs) in a physical housing of the respective radio unit. Each radio unit also includes a fronthaul interface configured to communicate with the at least one baseband controller using a packet-based protocol on behalf of each VRU. Each radio unit also includes at least one radio frequency front end unit configured to transmit from and receive on behalf of each of the VRUs.
Dual-duplex link with independent transmit and receive phase adjustment
A Serializer/Deserializer (SERDES) circuit is disclosed. The circuit includes an input/output (I/O) pad for coupling to a duplex SerDes link. An adjustable delay line provides a first component of a relative phase between a receive signal sampling point and a transmit echo signal. A second delay circuit generates a second component of the relative phase. A timing relationship between the receive signal sampling point and the transmit echo signal is based on the sum of the first and second components.
Method and apparatus for crest factor reduction
A method and apparatus in a communication system. The method includes: detecting multiple signal peaks of a target exceeding a predetermined threshold magnitude set to constitute one or more peak clusters; generating one or more noise shaping pulse clusters; assigning one or more noise shaping pulse clusters to the detected signal peaks in one or more peak clusters to clip the detected signal peaks in frequency domain; calculating an output signal based on the clipped signal peaks; the noise shaping pulse cluster comprises multiple sub-noise shaping pulses, bandwidths of the multiple sub-noise-shaping pulses are overlapped and a bandwidth of the noise shaping pulse cluster is greater than the bandwidth of the target signal.
Frequency-shaped digital predistortion
Various examples are directed to a digital predistortion (DPD) circuit comprising a DPD actuator circuit, a DPD feedback frequency-shaping filter, a basis matrix generator circuit, a basis matrix frequency-shaping filter, and a DPD adaption circuit. The DPD actuator circuit may generate a predistorted signal based at least in part on an input signal and a set of frequency-shaped DPD parameters. The DPD feedback frequency-shaping filter may filter a DPD feedback signal to generate a frequency-shaped DPD feedback signal. A passband of the DPD feedback frequency-shaping filter may include substantially all of a bandwidth of the input signal and exclude a distortion term outside the bandwidth of the input signal. The basis matrix generator may generate a basis matrix based at least in part on a power amplifier feedback signal The basis matrix frequency-shaping filter may generate a frequency-shaped basis matrix based at least in part on the basis matrix. The DPD adaption circuit may be configured to generate the set of frequency-shaped DPD parameters based at least in part on the frequency-shaped basis matrix and the frequency-shaped DPD feedback signal.
METHOD FOR REDUCING PEAK-TO-AVERAGE POWER RATIO PAPR, AND COMMUNICATION APPARATUS
Embodiments of this application disclose a method for reducing a peak-to-average power ratio PAPR, and a communication apparatus, and are applied to a transmitting system including a power amplifier. In the method, a reserved resource may be determined based on a first unscheduled resource in transmission bandwidth and/or a second unscheduled resource in guard bandwidth, and a fixed reserved resource in a conventional technology does not need to be used. Therefore, flexibility of determining the reserved resource can be improved, and flexibility of reducing a peak-to-average power ratio PAPR in a frequency domain resource reservation TR manner can further be improved.
CLOCK AND DATA RECOVERY CIRCUIT AND FEED FORWARD EQUALIZER DECOUPLING
A receiver includes an analog-to-digital converter (ADC) to generate a digital output, including a set of bits corresponding to a received signal. The receiver further includes a calculator circuit coupled to the ADC, the calculator circuit to calculate a set of tap coefficient gradient values corresponding to the digital output, generate a first feedback signal corresponding to the set of tap coefficient gradient values, and generate a second feedback signal corresponding to the set of tap coefficient gradient values. The receiver further includes a clock data recovery (CDR) circuit, coupled to the calculator circuit, the CDR circuit to detect a first parameter of the received signal based on the first feedback signal. The receiver further includes a feed forward equalization (FFE) system, coupled to the calculator circuit, the FFE system including multiple filter taps having a set of filter tap coefficients to be adapted based on the second feedback signal to generate a set of adapted filter tap coefficients
Changing settings for a transient period associated with a deterministic event
Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link. The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.
Clock and data recovery circuit and feed forward equalizer decoupling
A receiver includes an analog-to-digital converter (ADC) to generate a digital output, including a set of bits corresponding to a received signal. The receiver further includes a calculator circuit coupled to the ADC, the calculator circuit to calculate a set of tap coefficient gradient values corresponding to the digital output, generate a first feedback signal corresponding to the set of tap coefficient gradient values, and generate a second feedback signal corresponding to the set of tap coefficient gradient values. The receiver further includes a clock data recovery (CDR) circuit, coupled to the calculator circuit, the CDR circuit to detect a first parameter of the received signal based on the first feedback signal. The receiver further includes a feed forward equalization (FFE) system, coupled to the calculator circuit, the FFE system including multiple filter taps having a set of filter tap coefficients to be adapted based on the second feedback signal to generate a set of adapted filter tap coefficients.
Equalizer For Limited Intersymbol Interference
Disclosed is a mechanism for limiting Intersymbol Interference (ISI) when measuring uncorrelated jitter in a test and measurement system. A waveform is obtained that describes a signal. Such waveform may be obtained from memory. A processor then extracts a signal impulse response from the waveform. The processor selects a window function based on a shape of the signal impulse response. Further, the processor applies the window function to the signal impulse response to remove ISI outside a window of the window function while measuring waveform jitter. The window function may be applied by applying the window function to the signal impulse response to obtain a target impulse response. A linear equalizer is then generated that results in the target impulse response when convolved with the signal impulse response. The linear equalizer is then applied to the waveform to limit ISI for jitter measurement.