A processing module for a receiver device is disclosed. The processing module is configured to provide for processing of a signal received by the receiver device from a transmitter device. The signal includes a secure training sequence divided into a plurality of time spaced blocks. The secure training sequence incoudes a non-repeating pattern of symbols. The processing module is configured to, based on a first phase marker in the first block and a second phase marker in the second block defining a phase difference of the signal between the first and second antennas and a known spacing of the first antenna relative to the second antenna, determine an angle of arrival of the signal relative to the receiver device.

The disclosure relates to a processing module of a receiver device and associated method and apparatus. The method comprises receiving a signal comprising one or more frames, each frame comprising a synchronization-symbol-portion, a security-sequence-portion, and a data-payload-portion; and processing the signal to perform carrier recovery, and excluding at least part of the security-sequence-portions of the one or more frames from the carrier recovery process.

A signal receiving apparatus includes a phase recovery look, a phase estimation circuit, a phase noise detection circuit, and a bandwidth setting circuit. The phase recovery loop performs a phase recovery process on an input signal according to a bandwidth setting. The phase estimation circuit generates an estimated phase associated with the input signal. The phase noise detection circuit determines a phase noise amount according to the estimated phase. The bandwidth setting circuit calculates an average and a variance of the phase noise amounts, and adjusts the bandwidth setting of the phase recovery loop according to the average and the variance.

The disclosure relates to a processing module of a receiver device and associated method and apparatus. The method comprises receiving a signal comprising one or more frames, each frame comprising a synchronization-symbol-portion, a security-sequence-portion, and a data-payload-portion; and processing the signal to perform carrier recovery, and excluding at least part of the security-sequence-portions of the one or more frames from the carrier recovery process.

A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N(P/2)=M, L>QM, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.

A processing module for a receiver device is disclosed. The processing module is configured to provide for processing of a signal received by the receiver device from a transmitter device. The signal includes a secure training sequence divided into a plurality of time spaced blocks. The secure training sequence incoudes a non-repeating pattern of symbols. The processing module is configured to, based on a first phase marker in the first block and a second phase marker in the second block defining a phase difference of the signal between the first and second antennas and a known spacing of the first antenna relative to the second antenna, determine an angle of arrival of the signal relative to the receiver device.

A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N(P/2)=M, L>QM, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.