A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.

Methods, apparatus, systems and articles of manufacture for wideband and fast chirp generation for radar systems are disclosed herein. An example apparatus includes a phase digital-to-analog converter to convert a digital input that specifies at least one of a phase modulation or a frequency modulation into an analog output, and to generate a phase modulated output centered on an intermediate frequency. The example apparatus also includes a frequency multiplier to frequency multiply the phase modulated output centered on the intermediate frequency by a multiplication factor to generate a chirp signal.

An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 W with a sensitivity of 72 dBm at a BER of 10.sup.3 and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.

The present invention relates to a method for high-speed parallel processing for an ultrasonic signal, the method used for generation of an ultrasonic image by a smart device, which is provided with a mobile graphic processing unit (GPU), by receiving an input of an ultrasonic signal. The method comprises the steps of: receiving an input of an ultrasonic signal beam-formed by means of a first rendering cycle, removing a DC component from the ultrasonic signal, and then separating an in-phase component and a quadrature component from the ultrasonic signal, from which the DC component has been removed, and separately outputting same; a smart device performing quadrature demodulation and envelope detection processing for the ultrasonic signal, having the in-phase component and the quadrature component, by means of a second rendering cycle; and the smart device performing scan conversion for the ultrasonic signal, which has been obtained as the result of the second rendering cycle, by means of a fifth rendering cycle, wherein the rendering cycles are formed as a graphics pipeline structure comprising a vertex shader procedure, a rasterizer procedure, and a fragment shader procedure. A method for high-speed parallel processing for an ultrasonic signal by using a smart device, according to the present invention, enables high-speed parallel processing for an ultrasonic signal by means of a mobile GPU inside a smart device even in a mobile-based environment instead of a PC-based environment, thereby enabling the providing of an image having a frame rate that is useful for medical diagnosis.

An in-phase (I) and quadrature (Q) demodulator includes an input for receiving a signal, a reference frequency source, and a sampler connected with the input. The sampler includes a sampler strobe connected with the reference frequency source, and a non-linear transmission line (NLTL) connected with the sampler strobe. The NLTL receives a strobe signal generated by the sampler strobe and multiplies a frequency of the strobe signal to generate a sampler signal. When the sampler receives a signal from the input, the sampler is configured to generate and output an intermediate frequency (IF) signal using the sampler signal. A splitter of the demodulator separates the IF signal into an in-phase (I) component and a quadrature (Q) component. Mixers receive the I and Q components and generate I and Q output signals shifted 90 in phase.

An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 W with a sensitivity of 72 dBm at a BER of 10.sup.3 and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.

A quadrature detection unit subjects an FM signal to quadrature detection using a local oscillation signal and outputs a base band signal. A first correction unit and a second correction unit correct the base band signal using a DC offset correction value. A DC offset detection unit subjects the corrected base band signal to rectangular to polar conversion and derives the DC offset correction value such that amplitudes in a plurality of phase domains defined in an IQ plane approximate each other. An FM detection unit subjects the corrected base band signal to FM detection and generates a detection signal. An addition unit adds an offset to the detection signal. An AFC unit generates a control signal for controlling a frequency of a local oscillation signal based on the detection signal to which the offset is added.

This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

A coherent detection-based high-speed chaotic secure transmission method includes: at a transmit terminal in a chaotic secure transmission system, optically coupling an optical chaotic carrier and transmission information by using an orthogonal basis to mask the transmission information by using a noise-like feature of the chaotic carrier, so as to obtain a chaotic masked signal; adding a fast phase disturbance and a fast polarization disturbance to the chaotic masked signal and transmitting the chaotic masked signal over an optical fiber transmission link; and at a receive terminal, obtaining the chaotic masked signal through coherent detection, compensating the chaotic masked signal for linear and nonlinear effects through digital signal processing, and using a polarization orthogonal basis- or phase orthogonal basis-based chaotic decryption algorithm to separate the chaotic carrier from the signal so as to complete decryption.

Apparatus for determining a time of arrival of a message signal comprising: a quadrature mixer (13, 14) for mixing a received message signal with the signal of a local oscillator, wherein the received message signal comprises a binary sequence modulated by binary frequency shift keying with pulses corresponding to a first value at a first frequency and with pulses corresponding to a second value at a second frequency, wherein the local oscillator has a frequency between the first frequency and the second frequency; a time of arrival detector (18) for determining a time of arrival of the message signal on the basis of the output of the quadrature mixer (13, 14).