A receiver receives binary information from a transmission using a binary amplitude shift keying where information symbols are represented by a signal including a first power state and a second power state. A duration of a bit includes a first part where the second power state is applied irrespective of which binary value is represented, and a second part where a binary value is represented by any of the first power and a third power state or a combination pattern of the first power state and the third power state. A sampling circuit is arranged to retrieve samples of the received signal during the second part and discard samples during the first part. A duration of the retrieving of samples is selected to be a time corresponding to the duration of the second part plus a time based on an expected synchronization error.

A communication device having a radio receiver configured to receive a radio signal, a sampling circuit configured to sample the radio signal to generate a sequence of digital sampling values of the radio signal, a correlator configured to correlate the sequence of digital sampling values with each of a plurality of sequences of reference signal values, wherein each sequence of reference signal values corresponds a respective radio communication technology of a plurality of radio communication technologies, a controller configured to select a radio communication technology of the plurality of radio communication technologies based on the results of the correlation, and a data recovery circuit configured to demodulate and decode the radio signal according to the selected radio communication technology.

A device can comprise a peaked integrator circuit that generates an output signal from a continuous time signal based on a sub rate clock timing cycle. The device can further comprise a track and hold circuit coupled to the output of the peaked integrator that generates a held discrete time signal from the output of the peaked integrator based on a second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval. The device can further comprise an integrator circuit coupled to an output of the track and hold circuit that integrates the held discrete time signal, based on the second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval.

A method of transporting digital data in an active distributed antenna system DAS. The method includes receiving data from at least one data source, processing the received data, and providing the processed data as digital real-valued passband data for further transport within the DAS. An apparatus and computer program configured to perform the method are also provided.

A receiver device includes an I-Q mixer circuit configured to provide an I-phase signal and a Q-phase signal. The receiver device also includes a first analog-to-digital converter (ADC) circuit configured to digitize the I-phase signal. The receiver device also includes a second ADC circuit configured to digitize the Q-phase signal. The receiver device also includes a 25% duty cycle clock generator configured to provide 25% duty cycle clock signals to the I-Q mixer. The 25% duty cycle clock generator includes a divider circuit with an inverter ring arrangement.

A receiver device includes an I-Q mixer circuit configured to provide an I-phase signal and a Q-phase signal. The receiver device also includes a first analog-to-digital converter (ADC) circuit configured to digitize the I-phase signal. The receiver device also includes a second ADC circuit configured to digitize the Q-phase signal. The receiver device also includes a 25% duty cycle clock generator configured to provide 25% duty cycle clock signals to the I-Q mixer. The 25% duty cycle clock generator includes a divider circuit with an inverter ring arrangement.

Devices and methods for estimation of quadrature signal imbalance are provided. A quadrature signal is coupled to a computing system. The computing system determines several points on a symmetry function of corrected quadrature signals, and identifies a symmetry point that may satisfy a threshold level. An imbalance corresponding to the identified symmetry point may be used as an imbalance estimate. The imbalance estimate can be used for imbalance correction. Multiple imbalance estimates can be combined to reduce random errors caused by noise. Triangulation can be used to identify a value of symmetry that satisfies a threshold level. Triangulation allows the determination of the location of a symmetry trough by calculating as few as four symmetry points, thereby permitting embodiments to track rapidly changing imbalance. The disclosed embodiments may be employed in optical velocimetry systems, detection and ranging systems such as radar, sonar, and lidar, ultrasonics, and communications systems.

The present disclosure provides a method for estimating a frequency offset, including: extracting sampling points from an input signal according to preset intervals to obtain a plurality of groups of sampling points, with the preset intervals of the groups of sampling points being different; performing processes on a current sampling point and the groups of sampling points to obtain data of arguments of complex numbers corresponding to the preset intervals; and determining an estimation value of a frequency offset of a current input signal according to the data of arguments of complex numbers corresponding to the preset intervals. The present disclosure further provides an apparatus for estimating a frequency offset, an electronic device and a computer-readable medium.

System and method of demodulation by adapting constellation values based on statistic distributions of received data symbols. To determine an adapted constellation, an expected ratio of received symbols with values in a certain range is preset based on an expected statistic distribution of data symbols across the multiple constellations. For a set of received symbols, a count ratio of symbols falling in a first range to all the symbols in the set is compared with the expected ratio, where the first range is defined as below a first value. The first value is repeatedly adjusted to adjust the first range until the count ratio equals the expected ratio. The final first value is then designated as the optimal adapted constellation.

A circuit for demodulating an input signal is described. The circuit may be configured to demodulate signals modulated with amplitude-based modulation schemes, such as amplitude shift keying (ASK). The demodulator may comprise a clock extractor configured to generate a clock signal in response to receiving an amplitude-modulated input signal, a phase shifter configured to generate a sampling signal by phase-shifting the clock signal by approximately /2, and a sampler configured to sample the input signal in correspondence to one or more edges (such as one or more falling edges) of the sampling signal. In this way, the amplitude-modulated input signal may be sampled at its peak, or at least near its peak, thus ensuring high signal fidelity.