Provided are a printed circuit board configured to achieve reduction in impedance of a differential transmission line extending in a stacking direction, and an optical module. The printed circuit board includes a stacking-direction differential transmission line extending in the stacking direction, including: a differential signal via pair including a first signal via and a second signal via; and a plurality of conductor plate pairs each including a first conductor plate expanding outward from the first signal via, and a second conductor plate expanding outward from the second signal via. With respect to a perpendicular bisector of a center-of-gravity line segment connecting centers of gravity of the first and second signal vias, in each of the plurality of conductor plate pairs, centers of gravity of contours of the first and second conductor plates are located on inner sides of the centers of gravity.

Back drilling vias of a PCB, including: identifying a particular diameter of a particular via of multiple vias of the PCB; back drilling of the particular via with a first drill bit having a first diameter, the first diameter a first percentage greater than the particular diameter of the particular via; determining whether the first diameter of the first drill bit is a threshold percentage greater than the particular diameter of the particular via; determining that the first diameter of the first drill bit is less than the threshold percentage greater than the particular diameter of the particular via, and in response: back drilling of the particular via with a second drill bit having a second diameter, the second diameter a second percentage greater than the particular diameter of the particular via, the second diameter greater than the first diameter.

The invention relates to an electric interface, in particular an interposer, having a first connection plane with at least one first contact surface pair, each of which has a first and second contact surface, and a second connection plane with at least one second contact surface pair, each of which has a third and a fourth contact surface. For each of a first and second contact surface pair, a first electric connection electrically connects the first contact surface of the first connection plane to the third contact surface of the second connection plane, and a second electric connection electrically connects the second contact surface of the first connection plane to the fourth contact surface of the second connection plane. The first electric connection between the first and third contact surface has a specified first geometric length, and the second electric connection between the second and fourth contact surface has a specified second geometric length, the first and second geometric length being different.

An electronic device disclosed herein includes a first conductor layer, a first nonconducting layer, and a second conductor layer in a stacked arrangement. A signal carrying conductive via is formed in the first nonconducting layer and extends between the first conductor layer and the second conductor layer. A shielding conductive via is formed in the first nonconducting layer, is not electrically coupled to the signal carrying conductive via, and substantially completely surrounds the signal carrying conductive via in spaced apart relation thereto.

A high-speed transmission circuit design reduces or eliminates the presence of unwanted stub-effects and avoids uncontrolled line impedances that in existing circuits cause impedance mismatches that give rise to unwanted reflections and, ultimately, degrade signal integrity, e.g., in belly-to-belly configurations involving Quad Small Form-Factor Pluggable Double Density (QSFP DD) connectors. In various embodiments, by preventing overcrowding of signal lines, the circuit design further reduces crosstalk and increases signal integrity.

An electrical component, such as an RF device or thermal bridge, for use with a printed circuit board. The component has a first dielectric layer having a top and a bottom, a first conductive trace positioned on the bottom of the dielectric layer, and a first ground layer positioned on the bottom of the dielectric layer and spaced apart from the first conductive trace. For RF applications, a second conductive trace is positioned on top of first dielectric, a second dielectric is positioned on top of the second conductive trace, and a second ground plane is positioned on top of the second dielectric. A printed circuit board having a third conductive trace may then be coupled to the first conductive trace by a first solder layer.

A circuit board includes: a first surface and a second surface opposite to the first surface; a through hole extending between the first surface and the second surface; a conductor covering an inner wall surface of the through hole, a first end and a second end of the conductor being terminated inside the through hole; and a wire connected to the conductor, wherein a sum of a length from a contact portion where the conductor contacts a connector pin inserted in the through hole to the first end of the conductor, and a length from a wire connecting portion where the conductor is connected to the wire to the second end of the conductor is 0.5 mm or less.

An apparatus comprising a stack of printed circuit board (PCB) layers having a primary longitudinal structure forming a radio frequency (RE) via including a principal tuning section (223) and a constant longitudinal structure (227) along a conductive column support (255) journaled through the layers in the via. The principal section (221) comprising a first tuning sub-assembly (229 A) in a first portion of the RE via above the longitudinal structure (227) and at an entrance of the primary longitudinal structure (221) and comprising a first set of pad, anti-pad pairs (445, 545, 645) tuned to receive an RE band. A second principal tuning sub-assembly (229B) in a second portion of the via below the longitudinal structure (227) and at an exit of the primary longitudinal structure and comprising a second set of pad, anti-pad pairs (445, 545, 645) tuned to receive the band and mirroring the first set of pairs.

A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

An antenna module includes a resin multilayer substrate including a plurality of base materials that are flexible. The resin multilayer substrate includes a rigid portion at which a first number of stacked layers of the base materials is relatively large and a flexible portion at which a second number of stacked layers of the base materials is relatively small. A radiating element including a conductor pattern is provided at the rigid portion. A transmission line including a conductor pattern and electrically connected to the radiating element is provided at the flexible portion. A frame-shaped conductor that surrounds the radiating element when viewed in a direction in which the base materials are stacked is provided at either the rigid portion or the flexible portion, or both the rigid portion and the flexible portion.