Patent classifications
H05K1/0253
Vertically transitioning between substrate integrated waveguides (SIWs) within a multilayered printed circuit board (PCB)
Methods and apparatuses for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB) are disclosed. A first substrate integrated waveguide (SIW) is provided in a first layer of the PCB, the first SIW having a first terminal portion. A second SIW is provided in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion, wherein a first ground plane separates the first SIW and the second SIW. A vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, such that a signal propagated in the first SIW transitions to the second SIW in a different layer through the aperture.
Reference metal layer for setting the impedance of metal contacts of a connector
A circuit board has an electrical circuit and a connector that is attached to the circuit board. The connector has metal contacts. A housing of the connector has an embedded reference metal layer that is disposed under a single-ended metal contact or differential metal contacts. The reference metal layer sets the impedance of the single-ended metal contact or the differential metal contacts.
Display device
A display device includes a display panel, a data driver which transmits a data voltage to the display panel, a first flexible printed circuit board attached to the display panel and including an input side wiring electrically connected to the data driver, a first printed circuit board (PCB) electrically connected to the input side wiring to transmit a high-speed driving signal to the data driver, and a metal tape overlapping the input side wiring in a plan view and attached on the first flexible printed circuit board, where a part of the metal tape overlapping the input side wiring in the plan view defines an opening.
Low loss high-speed interconnects
An electronic device and associated methods are disclosed. In one example, the electronic device can include an assembly having asymmetrically situated conductors. In selected examples, the assembly includes a ground plane, a central shield portion, a first side shield portion on a first side, a second side shield portion on a second side, a first conductor asymmetrically situated between the central shield portion and the first side shield portion, a second conductor asymmetrically situated between the central shield portion and the second side shield portion, and dielectric within the assembly.
Printed circuit board with substrate-integrated waveguide transition
In described examples, an integrated waveguide transition includes a substrate with a waveguide side and an opposing waveguide termination side. A first layer of metal covers a portion of the waveguide side, a second layer of metal is separated from the first layer of metal by a first layer of dielectric, and a third layer of metal covers a portion of the waveguide termination side and is separated from the second layer of metal by a second layer of dielectric. A substrate waveguide perpendicular to a plane of the substrate extends from the waveguide side to the waveguide termination side; and a length and a width of the substrate waveguide is defined by a fence of ground-stitching vias that short the first layer of metal and the second layer of metal to a plate of the third layer of metal that forms a back short.
REFERENCE METAL LAYER FOR SETTING THE IMPEDANCE OF METAL CONTACTS OF A CONNECTOR
A circuit board has an electrical circuit and a connector that is attached to the circuit board. The connector has metal contacts. A housing of the connector has an embedded reference metal layer that is disposed under a single-ended metal contact or differential metal contacts. The reference metal layer sets the impedance of the single-ended metal contact or the differential metal contacts.
Selective ground flood around reduced land pad on package base layer to enable high speed land grid array (LGA) socket
Embodiments include a transmission line-land grid array (TL-LGA) socket assembly, a TL-LGA socket, and a package substrate. The TL-LGA socket assembly includes a TL-LGA socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion. The housing body has a top surface and a bottom surface, where the top surface is a conductive layer. The TL-LGA socket assembly also includes a package substrate having a base layer having a signal pad and a ground strip. The base layer is above the conductive layer of the housing body of the TL-LGA socket. The ground strip is above the horizontal portion of the interconnect and adjacent to the signal pad. The horizontal portion is coupled to the signal pad on the base layer. The package substrate may have a pad with a reduced pad area.
Multilayer substrate, electronic device, and method of manufacturing multilayer substrate
A multilayer substrate includes a laminate, first and second signal lines, first and second ground conductors, and interlayer connection conductors. The first and second signal lines extend along a transmission direction and include parallel extending portions that extend in parallel or substantially in parallel with each other. The first and second ground conductors sandwich the first and second signal lines in a laminating direction. The first and second ground conductors respectively include a first opening and a third opening between the signal lines when viewed from the laminating direction, and respectively include second openings and fourth openings disposed outside in a width direction orthogonal or substantially orthogonal to the transmission direction in the parallel extending portions when viewed from the laminating direction. The interlayer connection conductors are disposed in the transmission direction and at least between the signal lines.
Single layer radio frequency integrated circuit package and related low loss grounded coplanar transmission line
A novel and useful a single layer RFIC/MMIC structure including a package and related redistribution layer (RDL) based low loss grounded coplanar transmission line. The structure includes a package molded around an RF circuit die with a single redistribution layer (RDL) fabricated on the surface thereof mounted on an RF printed circuit board (PCB) via a plurality of solder balls. Coplanar transmission lines are fabricated on the RDL to conduct RF output signals from the die to PCB signal solder balls. The signal trace transition to the solder balls are funnel shaped to minimize insertion loss and maximize RF isolation between channels. A conductive ground shield is fabricated on the single RDL and operative to shield the plurality of coplanar transmission lines. The ground shield is electrically connected to a ground plane on the PCB via a plurality of ground solder balls arranged to surround the plurality of coplanar RF transmission lines and signal solder balls, and are operative to couple the ground shield to the ground plane on the PCB and provide an electrical return path for the plurality of coplanar transmission lines. Ground vias on the printed circuit board can be either located under the ground solder balls or between them.
Reference metal layer for setting the impedance of metal contacts of a connector
A circuit board has an electrical circuit and a connector that is attached to the circuit board. The connector has metal contacts. A housing of the connector has an embedded reference metal layer that is disposed under a single-ended metal contact or differential metal contacts. The reference metal layer sets the impedance of the single-ended metal contact or the differential metal contacts.