A printed substrate forming method includes: a resin layer forming step of forming a resin layer with curable resin in a specific region that is a region other than a predetermined region of a base which is composed of an insulating layer and a conductor layer, the predetermined region of which being a region on which a solder resist is formed; and a wiring forming step of forming a wiring by discharging metal-containing liquid which contains metal fine particles onto a top surface of the resin layer, and firing the metal-containing liquid.

The present invention addresses the problem of providing a connecting structure or similar that can minimize a decrease in a wireable region of a substrate while reducing the effect of stubs of a pair of vias on the output of a capacitor that is connected to said vias. In order to solve this problem, this connecting structure comprises: a first conductor that passes through a substrate and is provided with a first input/output section; a second conductor that passes through the substrate and is provided with a second input/output section; a first capacitor, one terminal of which being connected to a terminal of the first conductor that is on a first surface of the substrate, the other terminal of which being connected to a terminal of the second conductor that is on the first surface of the substrate; and a second capacitor or a resistor.

A voltage determination device includes: a printed wiring board on which first to third substrate terminals are arranged in substantially one line; first and second voltage determination circuits mounted on the printed wiring board and disposed on a first side of the printed wiring board divided by a line passing through the first to third substrate terminals; a first printed wiring connecting the first substrate terminal and the first voltage determination circuit; a second printed wiring connecting the second substrate terminal and the first voltage determination circuit; a third printed wiring connecting the third substrate terminal and the second voltage determination circuit; and a fourth printed wiring connecting the second substrate terminal and the second voltage determination circuit, in which the first to fourth printed wirings are provided without intersecting each other and without bypassing a second side of the printed wiring board divided by the first arrangement line.

A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).

An electronic apparatus includes first and second packages. The first package includes a first semiconductor chip between opposing first and second surfaces of the first package, a plurality of terminals on the first semiconductor chip facing a first direction that is perpendicular to the first and second surface, the terminals including first input/output terminals and a second input/output terminal, and a plurality of bumps that are electrically connected to the plurality of first input/output terminals at positions that are directly below the first semiconductor chip in the first direction. The second package includes a second semiconductor chip provided on the second surface of the first package, a wire that electrically connects the second semiconductor chip to a conductor that is electrically connected to the second input/output terminal, and coating resin that covers the second surface of the first package, the second semiconductor chip and the wire.

Systems and methods are provided for reducing crosstalk between differential signals in a printed circuit board (PCB) using fine pitch vias. A pair of contact pads are on the top surface of the PCB and configured to couple a PCB component to the PCB, the contacts a first distance from each other. A first via of a plurality of vias is electrically coupled to a first contact of the pair of contacts and a second via is electrically coupled to a second contact, the first via and second via a second distance from each other, the second distance being less than current standards for minimum via pitch. Each via comprises a via pad on the top surface and a plated through-hole extending from the top surface to a termination point. A separator gap is between the first via and the second via.

A flexible circuit board is provided. The flexible circuit board includes a base film with an outer lead region defined on either one surface or the other surface and an outer lead provided in the outer lead region and connected to an electronic device, in which the outer lead includes a plurality of first outer leads and a plurality of second outer leads formed to be spaced apart from each other so as to face each other in the outer lead region, and in which the number of the plurality of first outer leads is greater than the number of the plurality of second outer leads.

A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).

To provide a wiring substrate, an electronic device, and an electronic module the size of which can be easily reduced and the strength of which can be maintained. A wiring substrate includes an insulation substrate and an electrical wiring structure. The insulation substrate includes a recess section in one surface. A frame portion of the insulation substrate that forms a side surface which connects an opened surface and a bottom surface of the recess section to each other includes a first conductive portion having a plate shape in the frame portion.

A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.