A method for manufacturing a dual conductor laminated substrate includes providing a first laminate including a first insulating layer and a first conductive layer; defining a first trace pattern including one or more traces in the first laminate; providing a second laminate including a second insulating layer and a second conductive layer; defining a second trace pattern including one or more traces in the second laminate; defining access holes in the second insulating layer; at least one of depositing and stenciling a conductive material in the access holes of the second insulating layer; and aligning and attaching the first laminate to the second laminate to create a laminated substrate.

An implantable electrical connecting device includes a first elastic multi-ply layer and a second elastic multi-ply layer. The first elastic multi-ply layer has a first electrically conductive layer and a plurality of first electrical contacts electrically conductively connected to the first electrically conductive layer of the first elastic multi-ply layer. The second elastic multi-ply layer has a first electrically conductive layer and a plurality of second electrical contacts electrically conductively connected to the first electrically conductive layer of the second elastic multi-ply layer. The second electrical contacts make contact with the first electrical contacts.

Forming, in a printed-wiring board, a via sufficiently filled without residual smear, for use in an insulating layer and the size of the via to be formed. A via of a printed-wiring board comprises a first filling portion which fills at least a center portion of a hole, and a second filling portion which fills a region of the hole that is not filled with the first filling portion. An interface which exists between the second and first filling portions, or an interface which exists between the second filling portion and an insulating layer and the first filling portion has the shape of a truncated cone comprising a tapered surface which is inclined to become thinner from a first surface toward a second surface, and an upper base surface which is positioned in parallel to the second surface and closer to the first surface than to the second surface.

A method includes providing an electrically conductive layer structure on top of an electrically insulating layer structure, forming a window in the electrically conductive layer structure and removing material of the electrically insulating layer structure below the window by a first laser beam, and subsequently removing further material of the electrically insulating layer structure below the window by a second laser beam having a smaller size than a size of the window.

A component carrier has a stack including a plurality of electrically insulating layer structures and at least one electrically conductive layer structure, wherein two of the at least two electrically insulating layer structures form a dielectric double layer made of two different materials; a through-hole extending through the double dielectric layer; and an electrically conductive material filling at least a part of the through-hole. A method of manufacturing a component carrier is also disclosed.

An electronic component embedded substrate includes a core structure including a first insulating body and core wiring layers and having a cavity and a stopper layer. An electronic component is disposed in the cavity. The stopper layer includes a first metal layer embedded in the first insulating body and having a portion of an inner surface exposed from the first insulating body, and a second metal layer disposed below the first metal layer and having at least a portion of an upper surface disposed as a bottom surface of the cavity. The cavity has an inner surface of the first metal layer and an inner surface of the first insulating body as a first wall surface and a second wall surface, respectively, and an inclination of the first wall surface is different from an inclination of the second wall surface.

Package to printed circuit board (PCB) transitions are described. In one aspect, a multi-layer PCB includes an external layer having a transition region configured to receive an electrical component and a clear routing region outside of the transition region. The PCB includes first via(s) that extend from the transition region to an inner trace routing layer. The trace routing layer is disposed between the external layer and the second inner trace routing layer. The first inner trace routing layer includes a transition area disposed under the transition region of the external layer, a clear routing area outside of the transition region, and a transmission line that connects a given first via to a second via for a second electrical component. The transmission line includes conductive trace(s) that each have a first width in the transition area and a second width, greater than the first width, in the clear routing area.

A low permeability laminate film includes one or more low moisture permeability homogeneous polymer films with a total thickness between 0.5 and ten mils without glass or ceramic fillers and with a moisture permeability measured at 37° C. and 100% RH of less than 2.6 E-05 atm.Math.cc.Math.mm/in.sup.2.Math.sec of air. The polymer film includes one of polychlorotrifluoroethylene, polytetrafluorethylene, fluorinated ethylene propylene, and perfluoro alkoxy alkane. The low permeability laminate film further includes a nanolaminate including alternate combinations of nanolaminate material that is selected from the group consisting of alumina, titanium dioxide, zirconium oxide, beryllium oxide, hafnium oxide, titanium oxide, silicon nitride, tantalum nitride, silica, parylene F, parylene AF-4, parylene HT® and PTFE (polytetrafluoroethylene). A resulting coated nanolaminate film has a moisture permeability less than an equivalent standard leak rate per square inch of 3.0 E-08 atm.Math.cc/in.sup.2.Math.sec of air.

A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure, a component embedded in the stack, and a via formed in the at least one electrically insulating layer structure along a horizontal path having a length being larger than a horizontal width.

A method for manufacturing a dual conductor laminated substrate includes providing a first laminate including a first insulating layer and a first conductive layer; defining a first trace pattern including one or more traces in the first laminate; providing a second laminate including a second insulating layer and a second conductive layer; defining a second trace pattern including one or more traces in the second laminate; defining access holes in the second insulating layer; at least one of depositing and stenciling a conductive material in the access holes of the second insulating layer; and aligning and attaching the first laminate to the second laminate to create a laminated substrate.