Implementations described and claimed herein provide thin film devices and methods of manufacturing and implanting the same. In one implementation, a shaped insulator is formed having an inner surface, an outer surface, and a profile shaped according to a selected dielectric use. A layer of conductive traces is fabricated on the inner surface of the shaped insulator using biocompatible metallization. An insulating layer is applied over the layer of conductive traces. An electrode array and a connection array are fabricated on the outer surface of the shaped insulator and/or the insulating layer, and the electrode array and the connection array are in electrical communication with the layer of conductive traces to form a flexible circuit. The implantable thin film device is formed from the flexible circuit according to the selected dialectic use.

A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

A package carrier includes a build-up circuit structure, a first insulation protective layer, a plurality of connection pads, and a plurality of metal balls. The build-up circuit structure has an upper surface. The first insulation protective layer is disposed on the upper surface of the build-up circuit structure and has a plurality of first openings. The connection pads are respectively disposed in the first openings of the first insulation protective layer and are structurally and electrically connected to the build-up circuit structure. Each of the connection pads has an arc-shaped groove. The metal balls are respectively disposed in the arc-shaped groove of the connection pads. The metal balls and the corresponding connection pads define a plurality of bump structures, and a plurality of top surfaces of the bump structures are on a same plane.

The present invention provides a method for producing a novel printed wiring board having much higher adhesion between a filler-containing insulating resin substrate and a plating film. The method comprises the steps of: subjecting a filler-containing insulating resin substrate to a swelling treatment; a roughening treatment; a reduction treatment; and electroless plating,
wherein the filler-containing insulating resin substrate after the reduction treatment is treated with a first treating solution and a second treating solution, and then is subjected to the electroless plating,
wherein the first treating solution has a pH of 7 or higher and comprises: at least one selected from the group consisting of ethylene-based glycol ether represented by CmH(2m+1)-(OC.sub.2H.sub.4)n-OH, where m=an integer of 1 to 4, n=an integer of 1 to 4, and propylene-based glycol ether represented by CxH(2x+1)-(OC.sub.3H.sub.6)y-OH, where x=an integer of 1 to 4, y=an integer of 1 to 3, and
wherein the second treating solution has a pH of 7.0 or higher and comprises an amine-based silane coupling agent.

Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject mater further discloses methods of electrolytic plating by controlling surface area of an anode.

A wiring substrate includes a substrate containing a resin as a main component and including a mixed layer in which the resin and a catalyst are mixed together; and a metal wire disposed to cover the mixed layer and being in contact with the catalyst. The wiring substrate with such a configuration can increase the adhesion of the metal wire to the substrate.

A surface finish for a printed circuit board (PCB) and semiconductor wafer includes a nickel disposed over an aluminum or copper conductive metal surface. A barrier layer including all or fractions of a nitrogen-containing molecule is deposited on the surface of the nickel layer to make a barrier layer/electroless nickel (BLEN) surface finish. The barrier layer allows solder to be reflowed over the surface finish. Optionally, gold (e.g., immersion gold) may be coated over the barrier layer to create a nickel/barrier layer/gold (NBG) surface treatment. Presence of the barrier layer causes the surface treatment to be smoother than a conventional electroless nickel/immersion gold (ENIG) surface finish. Presence of the barrier layer causes a subsequently applied solder joint to be stronger and less subject to brittle failure than conventional ENIG.

A method of manufacturing a printed circuit board includes providing an insulating layer, forming a plating seed layer on the insulating layer, forming a first circuit pattern on the plating seed layer and a second circuit pattern on the first circuit pattern, and forming a top metal layer on the second circuit pattern. The second circuit pattern can be thinner than the first circuit pattern, and the top metal layer can be wider than the second circuit pattern.

A method of manufacturing a metal fabric or membrane, the method comprises providing an ink comprising a plurality of semiconductor particles disposed in a first solvent. The method comprises applying the ink to a fabric or membrane to obtain a fabric or membrane comprising a plurality of semiconductor particles. Finally, the method comprises contacting the fabric or membrane comprising the plurality of semiconductor particles with a deposition solution comprising a second solvent, an autocatalytic agent, and metal cations to thereby cause a reaction to occur such that the metal cations are reduced and at least partially displace the semiconductor particles, to thereby provide a metal fabric or membrane.

The present invention provides a conductive fabric comprising base cloth and a conductive metallic circuit structure formed on the surface of the base cloth. The conductive metallic circuit structure comprises at least one metallic seed layer and at least one chemical-plating layer. The metallic seed layer is an evaporation-deposition layer or a sputter-deposition layer and has a circuit pattern. The chemical-plating layer is applied over the surface of the metallic seed layer. The conductive fabric has improved conductivity and heat generation efficiency.