A printed circuit board includes a plurality of dielectric layers, a plurality of conductive pattern layers, a first through hole, a second through hole, and an inner layer via. The inner layer via penetrates through each dielectric layer from an Mth dielectric layer to the (N-1)th dielectric layer, where M is an integer that is greater than equal to two and less than or equal to (N-1) and has an inner circumferential surface on which an inner layer via conductor is disposed. At least a portion of the inner layer via is disposed in an inner via arrangement region. At least one of the first through hole and the second through hole is connected to the inner layer via with at least one conductive pattern layer that is selected from a second conductive pattern layer to an Nth conductive pattern layer in the plurality of conductive pattern layers.

A device includes an electrical board including a plurality of ball grid arrays (BGA) groups. Each BGA group of the plurality of BGA groups includes its respective BGA balls connected to its respective vias configured to route electrical signals between an integrated circuit to the electrical board. Vias for two adjacent BGA group of the plurality of BGA groups connect to different layers of the plurality of layers of the electrical board.

Disclosed herein are a printed circuit board and a method of making a printed circuit board. The printed circuit board includes a top surface having a top metal layer; a bottom surface having a bottom metal layer; a first through hole extending from the top surface to the bottom surface; and a first through connection disposed inside the first through hole and coupled to the top metal layer and the bottom metal layer, the first through connection including a first wall segment and a second wall segment that is separated from the first wall segment along a through direction of the first through hole. The method includes forming a through hole in the printed circuit board; disposing a through connection in the through hole; separating the through connection into a plurality of wall segments; and disposing dielectric columns among the plurality of wall segments.

A printed wiring board includes a first conductor layer, a resin insulating layer formed on the first conductor layer, a second conductor layer formed on the resin insulating layer and including a seed layer and a metal layer on the seed layer, a via conductor formed in the resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer, and a base layer formed on the resin insulating layer and including resin and one of iron and chromium in a range of 0.2 at % to 5.0 at % with respect to the resin such that the base layer includes part formed between the resin insulating layer and the seed layer.

An apparatus includes a printed circuit board (PCB), a solder pad, a signal via, a plurality of metalized vias, and a waveguide. The PCB has a first surface opposite a second surface and includes a first metal layer, a second metal layer having a waveguide opening, and a PCB channel region from the waveguide opening in the second metal layer to the second surface. The solder pad is positioned on the first surface of the PCB over the channel region, and the signal via is coupled to the solder pad and a via pad in the second metal layer within the waveguide opening. The plurality of metalized vias extend from the first surface to the second surface of the PCB and form a boundary around the channel region. The waveguide is affixed to the waveguide opening in the second metal layer.

An electronic device according to an embodiment includes first and second substrates, first and second conductors, and an electronic component. The first substrate includes a first connector portion, first pad portions, and a first transmission line. The first pad portions include a second pad portion, the first transmission line coupling the second pad portion and the first connector portion. The second substrate includes third pad portions. The third pad portions include a fourth pad portion and a fifth pad portion. The first conductor is coupled to the fourth pad portion and to the second pad portion. The second conductor is coupled to the fifth pad portion. The first electronic component has one end coupled to the first conductor and other end coupled to the second conductor.

A wiring substrate includes a first resin insulating layer having a cavity, a second resin insulating layer formed on the first insulating layer, a component accommodated in the cavity of the first insulating layer and including an electrode facing the second insulating layer, and a third resin insulating layer formed on the first insulating layer. The second insulating layer closes first-surface-side opening of the cavity in the first insulating layer and is closer to a mounting surface of an electronic component than the third insulating layer, the third insulating layer closes second-surface-side opening of the cavity in the first insulating layer and includes a part filling a gap formed between an inner wall of the cavity and the component in the cavity, and the cavity has a trapezoidal cross-sectional shape having a distance between opposing legs decreasing from the second surface toward the first surface of the first insulating layer.