In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

The present disclosure provides a printed circuit board and a wire arrangement method thereof. The printed circuit board includes a packaged chip and at least two connectors, wires of the packaged chip that are connected to different connectors are distributed on different board layers; and when the packaged chip is connected to one of the connectors, a via is backdrilled to form a high-speed path from the packaged chip to the connector, and copper walls of board layers corresponding to other connectors are drilled out. The wires of the packaged chip that are connected to different connectors are distributed on different board layers. When the packaged chip is connected to one of the connectors, according to backdrilling of different depths, the via is backdrilled to form a high-speed path from the packaged chip to the connector, and copper walls of board layers corresponding to other connectors are drilled out.

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.

In a multilayer board, conductor layers include a first conductor layer including a mounting electrode on a positive main surface of an insulator layer located farthest in a Z-axis positive direction of insulator layers. One or more first interlayer connection conductors connect two of the conductor layers located on a positive main surface and a negative main surface of a first insulator layer. The one or more first interlayer connection conductors each include a first region and a second region with a lower thermal conductivity than the first region and located on a Z-axis negative direction side of the first region. The one or more first interlayer connection conductors include one or more large-area first interlayer connection conductors with a larger area than a second interlayer connection conductor when viewed in a Z-axis direction.

A circuit board according to an embodiment includes a first insulating layer; and a second insulating layer disposed on an upper surface of the first insulating layer, wherein the second insulating layer includes a cavity, and the cavity has a planar shape including a plurality of convex parts convex toward an inner direction of the second insulating layer.

A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

A composite device includes a substrate and a mounted component mounted on a surface of, or inside, the substrate. The substrate includes a first thermoplastic resin layer. A surface of the mounted component includes a second thermoplastic resin layer that includes a same or a similar material as that of the first thermoplastic resin layer. A bonding layer that bonds the second thermoplastic resin layer and the first thermoplastic resin layer together is provided between the second thermoplastic resin layer and the first thermoplastic resin layer.

A component-embedded board includes a multilayer board obtained by stacking resin layers and an electronic component in the multilayer board having terminal electrodes on at least one principal face. The resin layers include a first resin layer having a space to accommodate the electronic component and at least one first interlayer connector formed by solidifying a conductive paste outside each of at least three sides of a principal face of the electronic component and a second resin layer having second and third interlayer connectors formed by solidifying a conductive paste. At least one second interlayer connector is positioned outside the three sides of the principal face. The third interlayer connectors are joined to the terminal electrodes. The first resin layer and the second resin layer are adjacent to each other in a stacking direction within the multilayer board. The first interlayer connector and the second interlayer connector are joined.