The present disclosure provides a method for manufacturing a semiconductor structure with capacitor landing pads. The method includes the following operations: providing a semiconductor substrate; forming a bit line structure protruding from the semiconductor substrate; depositing a landing pad layer to cover the bit line structure; planarizing a top surface of the landing pad layer; limning a trench in the landing pad layer to form the capacitor landing pads; forming an air gap within a sidewall of the bit line structure; and filling a first dielectric layer in the trench to seal the air gap.

A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.

A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

An embodiment of the application provides a method for forming a semiconductor structure. The semiconductor structure includes a first region and a second region. The method includes the following steps: providing a base, an insulating layer, and a mask layer that are stacked in sequence, where the first region has at least one trench penetrating the mask layer and the insulating layer, and the mask layer has an upper surface in the second region higher than that in the first region; forming a first protection layer, where an upper surface and a sidewall of the mask layer in the first region are covered with the first protection layer; after the first protection layer is formed, removing the mask layer in the second region; subsequent to removal of the mask layer in the second region, removing the first protection layer; and removing the mask layer in the first region.

An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.

Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer and a capacitor. Each of the first and second transistors includes a gate disposed on the substrate and source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and second transistors. The conductive layer is disposed above the first and second transistors and includes a circuit portion electrically connected to the first and second transistors and a dummy portion located above the isolation structure. The capacitor is disposed between the first and second transistors. The capacitor includes a body portion and first and second extension portions. The first and second extension portions extend from the body portion to the source/drain regions of the first and the second transistors, respectively. The first and second extension portions are disposed between the circuit portion and the dummy portion, respectively.

A method for forming a semiconductor device is disclosed. A substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer is provided. At least one capacitor cavity with corrugated sidewall surface is formed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is formed in the at least one capacitor cavity. The at least one buried capacitor comprises inner and outer electrodes with a capacitor dielectric layer therebetween. At least one transistor is formed on the substrate. The at least one transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one buried capacitor.

In a semiconductor structure preparation method, the trench runs through a well region of a first conductivity type and extends to the substrate below the well region. A heavily doped first electrode layer is formed on the sidewall of the trench. The first electrode layer covers the bottom of the trench and extends into the well region. A capacitor dielectric layer is formed on the surface of the first electrode layer and the sidewall of the trench, and a second electrode layer is formed on the surface of the capacitor dielectric layer to fill the trench. A dielectric layer is formed on the sidewall of the through silicon via, and an interconnect structure is formed on the surface of the dielectric layer to fill the through silicon via.

A semiconductor device includes a substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer. At least one capacitor cavity with corrugated sidewall surface is disposed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is provided in the at least one capacitor cavity. The at least one buried capacitor includes an inner electrode and an outer electrode with a capacitor dielectric layer therebetween.

A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a first oxide layer in the trench; forming a silicon layer on the first oxide layer; performing an oxidation process to transform the silicon layer into a second oxide layer; and planarizing the second oxide layer and the first oxide layer to form a shallow trench isolation (STI).