A semiconductor device according to the embodiments described herein includes a silicon carbide layer and a silicon oxide layer. The silicon oxide layer is disposed on the silicon carbide layer and contains at least one element selected from a group of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). In the silicon oxide layer, at least a part of the at least one element is single bonded to three oxygen atoms and double bonded to one oxygen atom.

The present invention provides a liquid crystal display device including: a liquid crystal panel including a viewing surface side substrate, a liquid crystal layer, and a back surface side substrate; and a backlight including a reflector facing the back surface side substrate, wherein the liquid crystal panel in a plan view includes multiple pixel regions and a non-display region between the pixel regions, in the pixel regions, color filters are disposed, in the non-display region, a gate electrode layer, a source-drain electrode layer, and a semiconductor layer are disposed, the back surface side substrate includes a reflective surface facing the backlight in at least part of the non-display region, and the reflective surface is constituted by a metal material having a higher reflectance than a metal material contained in portions of the source-drain electrode layer that are connected to the semiconductor layer.

A two-dimensional perovskite forming material with an ammonium halide group disposed on its surface can achieve a high carrier mobility. Preferably, the two-dimensional perovskite forming material includes a monolayer that has such an ammonium halide group at a terminal of its molecular structure, and the ammonium halide group in the monolayer is disposed in an ordered fashion on the surface of the material.

The present disclosure provides a method for manufacturing an array substrate, an array substrate, and a display device. The method for manufacturing the array substrate includes: forming a light-shielding layer and a buffer layer in sequence on a base substrate; forming an active layer on the buffer layer, and forming a first via hole in the active layer; forming an interlayer dielectric layer on the active layer; forming a second via hole in the interlayer dielectric layer at a position corresponding to the first via hole and a third via hole in the buffer layer at a position corresponding to the first via hole by a single patterning process; forming a source/drain electrode layer on the interlayer dielectric layer, in which the source/drain electrode layer is electrically connected to the light-shielding layer through the second via hole, the first via hole and the third via hole in sequence.

Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a D.sub.it of about 5e.sup.10 cm.sup.2eV.sup.1 to about 5e.sup.11 cm.sup.2eV.sup.1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

One aspect of this invention relates to an ohmic-contact-gated transistor (OCGT), comprising a bottom gate electrode formed on a substrate; a first dielectric layer formed on the bottom gate electrode; a thin film formed of a semiconducting material on the first dielectric layer; a bottom contact formed on a part of the thin film; a second dielectric layer conformally grown on the bottom contact to result in a self-aligned dielectric extension from the bottom contact on the thin film; and a top contact formed on the second dielectric layer on the top of the bottom contact and fully overlapping with the dielectric extension to define a device channel in the thin film under the dielectric extension between the bottom contact and the top contact.

A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.

A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.

The present disclosure provides a thin-film transistor having a plurality of carbon nanotubes in its active layer, its manufacturing method, and an array substrate. The manufacturing method as such comprises: forming an insulating layer to at least substantially cover a channel region of the active layer between a source electrode and a drain electrode of the thin-film transistor, wherein the insulating layer is configured to substantially insulate from an environment, and have substantially little influence on, the plurality of carbon nanotubes in the active layer.

The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate on the substrate; a dielectric layer on the gate, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer formed by magnetron sputtering and in direct contact with the gate; a semiconductor layer on the dielectric layer, wherein the semiconductor layer includes nano-scaled semiconductor materials; and a source and a drain, wherein the source and the drain are on the dielectric layer, spaced apart from each other, and electrically connected to the semiconductor layer. The thin film transistor almost has no current hysteresis.