A method for enhancing the performance of pentacene organic field-effect transistor (OFET) using n-type semiconductor interlayer: an n-type semiconductor thin film was set between the insulating layer and the polymer electret in the OFET with the structure of gate-electrode/insulating layer/polymer/pentacene/source (drain) electrode. The thickness of n-type semiconductor layer is 1˜200 nm. The induced electrons at the interface of n-type semiconductor and polymer electret lead to the reduction of the height of the hole-barrier formed at the interface of polymer and pentacene, thus effectively reducing the programming/erasing (P/E) gate voltages of pentacene OFET, adjusting the height of hole barrier at the interface of polymer and pentacene to a reasonable scope by controlling the quantity of induced electrons in n-type semiconductor layer, thus improving the performance of pentacene OFET, such as the P/E speeds, P/E endurance and retention characteristics.

In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

The present invention relates to a graphene transistor comprising: a substrate; a graphene channel layer arranged on the substrate; a pair of metals spaced from each other and respectively arranged at opposite ends of the graphene channel layer; and a linker layer arranged on the graphene channel layer and including an N-heterocyclic carbene compound, a fabrication method therefor, and a biosensor comprising the same. The graphene transistor according to the present invention in which the carbene group of the N-heterocyclic carbene compound forms a covalent bond with the graphene channel layer to modify the whole surface of the graphene channel layer exhibits excellent electric conductivity as a transistor and a biosensor comprising the transistor is improved in selectivity and sensitivity.

A graphene semiconductor junction device, having a structure in which a graphene edge does not come into contact with a semiconductor, includes: a substrate; a gate electrode positioned on the substrate; a gate insulating layer that is positioned on the substrate to cover the gate electrode; a graphene layer positioned on the gate insulating layer; a semiconductor layer that is positioned on the graphene layer so as not to be joined to an edge of the graphene layer; a drain electrode positioned on the semiconductor layer; and a source electrode that is positioned on the graphene layer to be separated from the semiconductor layer.

A method comprising: providing a substrate comprising one or more electronic structures; providing a layer of perovskite overlaying the one or more electronic structures; coating a layer of photoresist material overlaying the layer of perovskite; aligning a mask with the one or more electronic structures and patterning the photoresist material; and using the same etchant to remove sections of the patterned photoresist material and the perovskite underneath the sections of the photoresist material.

A flexible display substrate for a foldable display apparatus, a method of manufacturing the flexible display substrate, and a foldable display apparatus are disclosed. The flexible display substrate includes: a first region corresponding to a non-foldable region of the foldable display apparatus; a second region corresponding to a foldable region of the foldable display apparatus; a plurality of first pixel units disposed in the first region, configured to display an image, and each including a polysilicon thin film transistor; and a plurality of second pixel units disposed in the second region, configured to display an image, and each including an organic thin film transistor.

A layer according to one embodiment of the present invention may exhibit a first number of electron states in a low-level electron energy range in a conduction band, and exhibit a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band, wherein localized states may exist between the low-level electron energy range and the high-level electron energy level.

A multi-negative differential transconductance device includes a substrate conductive portion; a gate insulating layer formed by being laminated on the substrate conductive portion; a first semiconductor, a second semiconductor, and a third semiconductor which have different threshold voltages and are formed to be horizontally connected in series on the gate insulating layer; and an electrode formed at both ends of the first semiconductor and the third semiconductor. The multi-negative differential transconductance device forms a junction of three or more semiconductor materials in one device to have a plurality of peaks and valleys so that the multi-negative differential transconductance device is utilized to implement a multi-valued logic circuit which is capable of representing four or more logical states without significantly increasing an area of the negative differential transconductance device which occupies the chip. Therefore, effects of low power consumption, a reduced size, and high speed of a chip may be achieved.

A layer according to one embodiment of the present invention may exhibit a first number of electron states in a low-level electron energy range in a conduction band, and exhibit a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band, wherein localized states may exist between the low-level electron energy range and the high-level electron energy level.

A thin film transistor according to the inventive concept includes: a substrate; an insulating layer provided on the substrate; a superlattice channel layer provided on the insulating layer; and a source electrode and a drain electrode configured to cover a pair of opposite lateral surfaces of the superlattice channel layer, wherein the superlattice channel layer includes alternately stacked semiconductor layers and organic layers. A thickness of each semiconductor layer may be greater than about 3 nm to less than about 5 nm, and a thickness of each organic layer may be about 1 Å to about 1 nm.