A PPTC device is provided. The PPTC device may include a first electrode and a second electrode, disposed opposite the first electrode. The PPTC device may include a PPTC layer, disposed between the first electrode and the second electrode, the PPTC layer comprising a polymer matrix formed from a thermoplastic polyurethane (TPU) material.

A lead-free insulating ceramic coating zinc oxide arrester valve and a method for manufacturing thereof are disclosed. In an embodiment a method includes preparing an initial powder from starting materials with the following mass percentages: ZnO: 86-95%; Bi.sub.2O.sub.3: 1.0-3.0%; Co.sub.3O.sub.4: 0.5-1.5%; Mn.sub.3O.sub.4: 0.2-1.0%; Sb.sub.2O.sub.3: 3.0-9.0%; NiO: 0.2-1.0%; and SiO.sub.2: 1.0-3.0%, preparing a ceramic coating powder by mixing the initial powder, deionized water and first grinding balls, milling the mixture, and drying and pulverizing the mixture, preparing a ceramic coating slurry by mixing a PVA solution, the ceramic coating powder and second grinding balls and milling the mixture, applying the ceramic coating slurry to a green body, heating and debinding the ceramic coating slurry with the green body thereby forming a resistor element and sintering the resistor element thereby obtaining a zinc oxide surge arrester valve block having a lead-free insulating ceramic coating.

A varistor includes a sintered body, an internal electrode, an insulating layer, and an external electrode. The internal electrode is disposed in an interior of the sintered body. The insulating layer covers at least part of the sintered body and includes Zn.sub.2SiO.sub.4. The external electrode is electrically connected to the internal electrode, covers part of the sintered body and part of the insulating layer, and is in contact with the part of the insulating layer. The insulating layer has a region being in contact with the external electrode, the region having a greater average thickness than a region of the insulating layer which is out of contact with the external electrode.

In an embodiment a method for manufacturing a multilayer varistor includes providing a first ceramic powder for producing a first ceramic material and at least one second ceramic powder for producing a second ceramic material, wherein the ceramic powders differ from each other in concentration of monovalent elements X.sup.+ by 50 ppmc(X.sup.+)5000 ppm, wherein X.sup.+=(Li.sup.+, Na.sup.+, K.sup.+ or Ag.sup.+), and wherein c denotes a maximum concentration difference occurring between an active region and a near-surface region of the multilayer varistor, slicking of the ceramic powders and forming of green films, partially printing of a part of the green films with a metal paste to form inner electrodes, stacking printed and unprinted green films, laminating, decarbonizing and sintering the green films and applying outer electrodes.

In one embodiment a varistor may include a ceramic body. The varistor may further comprise a multilayer coating disposed around the ceramic body. The multilayer coating may include a first layer comprising a phenolic material or a silicone material; and a second layer adjacent the first layer, the second layer comprising a high dielectric strength coating.

A method for producing an electrical component is disclosed. In an embodiment the method includes providing a carrier element providing a material having a temperature-dependent resistance, applying the material on a surface of the carrier element for producing a resistance layer on the carrier element and subsequently sintering the resistance layer for linking the resistance layer to the carrier element.

A polymer positive temperature coefficient (PPTC) material is provided. The PPTC material may include a polymer matrix that defines a PPTC body, and further includes a high temperature polymer. The PPTC material may include a conductive filler component, disposed in the polymer matrix, an arc suppressant, and a high temperature antioxidant, disposed in the polymer matrix.

An electrostatic discharge circuit may include a substrate, an N+ buried layer in the substrate, an n-type epitaxial layer on the N+ buried layer and the substrate, a first P region in an anode region of the n-type epitaxial layer, a first N+ region in the first P region, an N-well in a cathode region of the n-type epitaxial layer, a first P+ region in the N-well, and a second N+ region located in the N-well. The first N+ region may be located closer to the second N+ region than the first P+ region.

A resistive paste according to the present disclosure includes metal particles, insulating particles, glass particles, and a metal silicide. The metal particles include copper and nickel. The insulating particles include at least one of alumina, zirconia, zinc oxide, or boron nitride. A chip resistor according to the present disclosure includes a resistive element and a substrate. The resistive element includes the resistive paste as a material and is disposed on the substrate.

A method for producing an electrical component is disclosed. In an embodiment the method includes providing a carrier element providing a material having a temperature-dependent resistance, applying the material on a surface of the carrier element for producing a resistance layer on the carrier element and subsequently sintering the resistance layer for linking the resistance layer to the carrier element.