Patent classifications
H01L21/02016
Integrated circuits and molding approaches therefor
Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.
Indium phosphide substrate
Provided is an indium phosphide substrate which has suppressed sharpness of a wafer edge when polishing is carried out from the back surface of the wafer by a method such as back lapping. An indium phosphide substrate, wherein when planes A each parallel to a main surface are taken in a wafer, the phosphide substrate has an angle on the main surface side of 0<110 for all of the planes A where a distance from the main surface is 100 m or more and 200 m or less, wherein the angle is formed by a plane B, the plane B including an intersection line of an wafer edge with each of the planes A and being tangent to the wafer edge, and an plane of each of the planes A extending in a wafer outside direction, and wherein in a cross section orthogonal to the wafer edge, the indium phosphide substrate has an edge round at least on the main surface side, and the edge round on the main surface side has a radius of curvature R.sub.f of from 200 to 350 m.
Semiconductor Device Having a Defined Oxygen Concentration
A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.
INTEGRATED CIRCUIT WITH BACKSIDE STRUCTURES TO REDUCE SUBSTRATE WARP
Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.
INTEGRATED CIRCUITS AND MOLDING APPROACHES THEREFOR
Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.
METHOD OF PROCESSING WAFER
A wafer has a plurality of projected dicing lines on a face side thereof, a plurality of devices formed in respective areas demarcated on the face side of the wafer by the projected dicing lines, a plurality of grooves defined in the projected dicing lines, and a molding resin laid on the devices and embedded in the grooves. An outer circumferential portion of the molding resin is removed, exposing the molding resin embedded in the grooves. The molding resin embedded in the grooves exposed on an outer circumferential portion of the wafer is detected, and a laser beam is focused at a transversely central point on the molding resin embedded in the grooves. The laser beam is applied to the molding resin along the grooves, thereby forming dividing grooves in the wafer to allow the wafer to be divided into individual devices.
DEFORMATION CONTROL OF MANUFACTURING DEVICES USING FRONT-SIDE IRRADIATION
Disclosed systems and techniques are directed to improvement of semiconductor manufacturing. In one disclosed embodiment, the disclosed systems and techniques include depositing one or more films on a front surface of a substrate, forming a stress compensation layer (SCL) on the one or more deposited films, the SCL causing stress in the substrate to be changed, subjecting the SCL to a stress-mitigation beam to reduce deformation of the substrate, and adding one or more features to at least one of the one or more deposited films.
Integrated circuit with backside structures to reduce substrate warp
Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.
Method of manufacturing a semiconductor device including removing a relief layer from back surface of semiconductor chip
A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.
Protecting flip-chip package using pre-applied fillet
A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.