A method for manufacturing a wafer having a functional film, with an outer peripheral part of a top face of the wafer annularly exposed, the method including: spin-coating a high-viscosity coating material that contains a functional film constituent over the top face of the wafer to form a coating film; subsequently, supplying a cleaning liquid to the outer peripheral part of the top face of the wafer and kept rotated to remove the coating film on the outer peripheral part of the top face of the wafer; subsequently, heating the coating film on the wafer to form a fluidity suppressed film; subsequently, supplying a cleaning liquid to the outer peripheral part of the top face of the wafer having the fluidity suppressed film and kept rotated to remove the fluidity suppressed film on the top face of the wafer; and subsequently, heating the fluidity suppressed film on the wafer.

A backside metallized compound semiconductor device includes a compound semiconductor wafer and a metal layered structure. The compound semiconductor wafer includes a substrate having opposite front and back surfaces, and a ground pad structure formed on the front surface. The substrate is formed with a via extending from the back surface to the front surface to expose a side wall of the substrate and a portion of the ground pad structure. The metal layered structure is disposed on the back surface, and covers the side wall and the portion of the ground pad structure. The metal layered structure includes an adhesion layer, a seed layer, a gold layer, and an electroplated copper layer that are formed on the back surface in such order. The method for manufacturing the backside metallized compound semiconductor device is also disclosed.

A method of manufacturing a semiconductor device includes bonding a first wafer with a second wafer. The second wafer includes a substrate, an isolation structure in the substrate, a transistor on the substrate, and a interconnect structure over the second transistor. A first etching process is performed to form a first via opening and a second via opening in the substrate. The second via opening extends to the isolation structure, and the second via opening is deeper than the first via opening. A second etching process is performed such that the first via opening exposes the substrate. A third etching process is performed such that the first via opening and the second via opening exposes the interconnect structure, and the second via opening penetrates the isolation structure. A first via is formed in the first via opening and a second via is formed in the second via opening.

The present invention provides a testing substrate (W) for estimating stress in production substrates due to a substrate support, said testing substrate having a support surface (SS) divided into predefined portions, wherein the predefined portions comprise at least one first portion (1) having a first coefficient of friction being substantially uniform across the at least one first portion, and at least one second portion (2) having a second coefficient of friction being substantially uniform across the at least one second portion, wherein the second coefficient of friction is different to the first coefficient of friction. The present invention also provides a method for estimating stress in a substrate due to a substrate support and a system for making such an estimation.

A device includes a thinned semiconductor substrate having a first side and a second side opposite to the first side; and at least one radio frequency device at the first side, wherein the second side of the thinned semiconductor substrate is processed to reduce leakage currents or to improve a radio frequency linearity of the at least one radio frequency device through Bosch etching.

A system and method for sequential single-sided CMP processing of opposite facing surfaces of a silicon carbide (SiC) substrate are disclosed. A method includes urging a first surface of a substrate against one of plurality of polishing pads, wherein the plurality of polishing pads are disposed on corresponding ones of a plurality of rotatable polishing platens. The method includes transferring, using the first side of the end effector, the substrate from the substrate carrier loading station to a substrate alignment station. The method includes transferring, using the first side of the end effector, the substrate from the substrate alignment station to a substrate carrier loading station. The method includes urging a second surface of the substrate against one of the plurality of polishing platens.

An object is to provide a SiC wafer in which a detection rate of an optical sensor can improved and a SiC wafer manufacturing method.

The method includes: a satin finishing process S141 of satin-finishing at least a back surface 22 of a SiC wafer 20; an etching process 21 of etching at least the back surface 22 of the SiC wafer 20 by heating under Si vapor pressure after the satin finishing process S141; and a mirror surface processing process S31 of mirror-processing a main surface 21 of the SiC wafer 20 after the etching process S21. Accordingly, it is possible to obtain a SiC wafer having the mirror-finished main surface 21 and the satin-finished back surface 22.

The invention relates to methods of processing a wafer, having on one side a device area with a plurality of devices. In particular, the invention relates to a method which comprises providing a protective film, and applying the protective film to the side of the wafer being opposite to the one side, so that at least a central area of a front surface of the protective film is in direct contact with the side of the wafer being opposite to the one side. The method further comprises applying an external stimulus to the protective film during and/or after applying the protective film to the side of the wafer being opposite to the one side, so that the protective film is attached to the side of the wafer being opposite to the one side, and processing the one side of the wafer and/or the side of the wafer being opposite to the one side.

Provided a method of producing a carrier which make it possible to prevent the reduction in the flatness of a semiconductor wafer even if the semiconductor wafer is subjected to repeated double-side polishing procedures. The method of producing a carrier including a metal portion and a ring-shaped resin portion includes: a preparation step of preparing the metal portion and the resin portion (Step S1); a placement step of placing the resin portion in the retainer opening in the metal portion (Step S2); and a resin portion polishing step of polishing both surface of the resin portion (Step S4). The method includes, prior to the resin portion polishing step (Step S4), a production stage swelling step of swelling the resin portion placed in the retainer opening in the metal portion by impregnating the resin portion with a first liquid (Step S3).

A monocrystalline semiconductor wafers have an average roughness R.sub.a of at most 0.8 nm at a limiting wavelength of 250 μm, and an ESFQR.sub.avg of 8 nm or less given an edge exclusion of 1 mm. The wafers are advantageously produced by a method comprising the following steps in the indicated order: a) simultaneous double-side polishing of the semiconductor wafer, b) local material-removing processing of at least one part of at least one side of the semiconductor wafer using a fluid jet which contains suspended hard substance particles and which is directed onto a small region of the surface with the aid of a nozzle, wherein the nozzle is moved over that part of the surface which is to be treated in such a way that a predefined geometry parameter of the semiconductor wafer is improved, and c) polishing of the at least one surface of the semiconductor wafer.