The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Provided is a laser mark printing method and a method of producing a laser-marked silicon wafer that can reduce the machining strain left around dots constituting a laser mark. In a method of printing a laser mark having a plurality of dots on a silicon wafer, the plurality of dots are formed using laser light having a wavelength in the ultraviolet region.

An object of the present invention is to provide a novel technology capable of achieving high-quality SiC seed crystal, SiC ingot, SiC wafer and SiC wafer with an epitaxial film. The present invention, which solves the above object, is a method for producing a SiC seed crystal for growth of a SiC ingot, the method including a heat treatment step of heat-treating a SiC single crystal in an atmosphere containing Si element and C element. As described above, by heat-treating the SiC single crystal in an atmosphere containing the Si element and the C element, it is possible to produce a high-quality SiC seed crystal in which strain and crystal defects are suppressed.

A fabrication method of a semiconductor substrate includes: performing a chemical mechanical polishing process on a silicon carbide wafer; and performing a heating process on the silicon carbide wafer to remove a naturally formed oxide layer, to remove contaminants, to obtain a scratch-free surface, and to planarize, wherein the heating process includes: heating a chamber of a furnace and the silicon carbide wafer to T degrees Celsius for a time t, and introducing hydrogen, argon, nitrogen, or/and hydrogen chloride into the chamber; and then cooling down the furnace.

A semiconductor device includes a substrate, a gate structure on the substrate, and a gate contact in the gate structure. The gate structure includes a gate electrode extending in a first direction and a gate capping pattern on the gate electrode. The gate contact is connected to the gate electrode. The gate electrode includes a protrusion extending along a boundary between the gate contact and the gate capping pattern.

Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a SORI value of 2.5 μm or less, as measured with the back surface of the indium phosphide substrate facing upward.

A display device includes a display panel configured to display an image, the display panel including a first non-folding area; a second non-folding area; and a folding area disposed between the first non-folding area and the second non-folding area; and a window disposed on the display panel and including a folding portion overlapping the folding area of the display panel. The folding portion of the window includes a first substantially curved surface, a substantially flat surface extending from the first substantially curved surface; and a second substantially curved surface extending from the substantially flat surface.

A semiconductor component includes: a SiC semiconductor body; a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body, the trench having a conductive connection structure, a structure width at a bottom of the trench, and a dielectric layer covering sidewalls of the trench; a shielding region along the bottom and having a central section which has a lateral first width; and a contact formed between the conductive connection structure and the shielding region. The conductive connection structure is electrically connected to a source electrode. In at least one doping plane extending approximately parallel to the bottom, a dopant concentration in the central section deviates by not more than 10% from a maximum value of the dopant concentration in the shielding region in the doping plane. The first width is less than the structure width and is at least 30% of the structure width.

A manufacturing process of wafer thinning includes a step of wafer-grinding to grind a surface of a wafer to a first predetermined thickness, and a step of wafer-etching to etch the grinded face of the wafer with the first predetermined thickness to a second predetermined thickness.

A semiconductor substrate includes a surface having a groove. The groove includes an inner bottom surface and an inner wall surface. The inner wall surface has a depression. The depression has a depth from a direction along a surface of the inner wall surface to a width direction of the groove. The substrate being exposed to the inner wall surface.