The invention relates to a method of producing a substrate. The method comprises providing a workpiece having a first surface and a second surface opposite the first surface, and providing a carrier having a first surface and a second surface opposite the first surface. The method further comprises attaching the carrier to the workpiece, wherein at least a peripheral portion of the first surface of the carrier is attached to the first surface of the workpiece, and forming a modified layer inside the workpiece. Moreover, the method comprises dividing the workpiece along the modified layer, thereby obtaining the substrate, wherein the substrate has the carrier attached thereto, and removing carrier material from the side of the second surface of the carrier in a central portion of the carrier so as to form a recess in the carrier. The invention further relates to a substrate producing system for performing this method.

A process of preparing a wafer having a diameter of two inches or more, at least a surface of the wafer being formed from a group III nitride crystal, including preparing an alkaline or acidic etching liquid containing a peroxodisulfate ion as an oxidizing agent that accepts an electron, accommodating the wafer such that the surface of the wafer is immersed in the etching liquid such that the surface of the wafer is parallel with a surface of the etching liquid; and radiating light from the surface side of the etching liquid onto the surface of the wafer without agitating the etching liquid. First and second etching areas disposed at an interval from each other are defined on the surface of the wafer. In the process of radiating the light onto the surface of the wafer, the light is radiated perpendicularly onto surfaces of the first and second etching areas.

A silicon layer etchant composition and associated methods, the composition including about 1 wt % to about 20 wt % of an alkylammonium hydroxide; about 1 wt % to about 30 wt % of an amine compound; about 0.01 wt % to about 0.2 wt % of a nonionic surfactant including both a hydrophobic group and a hydrophilic group; and water, all wt % being based on a total weight of the silicon layer etchant composition.

Provided is a method of selectively etching a substrate comprising at least one cycle of: depositing a chemical precursor on a surface of the substrate to form a chemical precursor layer on the substrate, the substrate comprising a first portion and a second portion, wherein the first and the second portion are of a different composition; selectively removing the chemical precursor layer and at least a part of the first portion of the substrate; and repeating the cycle until the first portion of the substrate is substantially or completely removed, wherein deposition of the chemical precursor and selective removal of the chemical precursor layer and at least a part of the first portion of the substrate are performed under a plasma environment.

Adaptive endpoint detection is applied to delayering of a multi-layer sample utilizing a combination of dynamic and predetermined parameters. Tuned predetermined parameters, varying between layers of the sample, allow automated operation across multiple sites of a device. A semiconductor logic device is described, having a zone of thick metal layers and a zone of thin metal layers. The described techniques can be integrated with analysis operations and can be applied across a wide range of device types and manufacturing processes.

A method of preparing a silicon carbide wafer for subsequent epitaxial growth thereon is disclosed. The method comprises (a) placing the silicon carbide wafer onto a support table in a plasma processing chamber such that the surface of the silicon carbide wafer distal to the support table is unmasked; (b) establishing a flow of an etch gas mixture into the plasma processing chamber, wherein the etch gas mixture comprises molecular hydrogen, H.sub.2; and (c) generating a plasma from the etch gas mixture within the plasma processing chamber and using the plasma to etch the unmasked surface of the wafer so as to reduce the roughness of the unmasked surface.

Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a SORI value of 2.5 μm or less, as measured with the back surface of the indium phosphide substrate facing upward.

A process of preparing a wafer having a diameter of two inches or more, at least a surface of the wafer being formed from a group III nitride crystal, including preparing an alkaline or acidic etching liquid containing a peroxodisulfate ion as an oxidizing agent that accepts an electron, accommodating the wafer such that the surface of the wafer is immersed in the etching liquid such that the surface of the wafer is parallel with a surface of the etching liquid; and radiating light from the surface side of the etching liquid onto the surface of the wafer without agitating the etching liquid. First and second etching areas disposed at an interval from each other are defined on the surface of the wafer. In the process of radiating the light onto the surface of the wafer, the light is radiated perpendicularly onto surfaces of the first and second etching areas.

A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element.

The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.