Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a SORI value of 2.5 μm or less, as measured with the back surface of the indium phosphide substrate facing upward.

According to one embodiment, a semiconductor wafer is formed with a plurality of first regions each provided with a circuit element and a second region between the first regions. The semiconductor wafer includes a first structure in which a first embedding material is embedded in a first recess extending in a first direction perpendicular to a surface of a substrate. The first structure is between edges of the first regions and a third region that is cut in the second region when the first regions are separated.

Semiconductor processing methods and apparatuses are provided. Some methods include providing a first wafer to a processing chamber, the first wafer having a thickness, a beveled edge, a first side, and a plurality of devices formed in a device area on the first side, the device area having an outer perimeter, depositing an annular ring of material on the first wafer, the annular ring of material covering a region of the beveled edge and the outer perimeter of the device area, and having an inner boundary closer to the center point of the first wafer than the outer perimeter, bonding a second substrate to the plurality of devices and to a portion of the annular ring of material, and thinning the thickness of the first wafer.

A semiconductor device including a semiconductor substrate, a first interlayer insulating layer arranged on the semiconductor substrate, a low dielectric layer arranged on the first interlayer insulating layer, a second interlayer insulating layer and a third interlayer insulating layer sequentially arranged on the low dielectric layer, and a through silicon via penetrating the semiconductor substrate and the first interlayer insulating layer, wherein the semiconductor substrate, the first interlayer insulating layer, and the low dielectric layer constitute a chamfered structure including a first chamfered surface parallel to the top surface of the semiconductor substrate and a second chamfered surface inclined with respect to the top surface of the semiconductor substrate and connected to the first chamfered surface may be provided.

Provided is an indium phosphide substrate, a method for manufacturing indium phosphide substrate, and a semiconductor epitaxial wafer capable of suppressing cracks in indium phosphide substrates caused by edge irregularities and processing damage. An indium phosphide substrate, wherein a surface roughness of an edge part of the substrate has a maximum height Sz of 2.1 μm or less, as measured by a laser microscopy on the entire surface of the edge part.

A method for processing a crystalline substrate to form multiple patterns of subsurface laser damage facilitates subsequent fracture of the substrate to yield first and second substrate portions of reduced thickness. Multiple (e.g., two, three, or more) groups of parallel lines of multiple subsurface laser damage patterns may be sequentially interspersed with one another, with at least some lines of different groups not crossing one another. Certain implementations include formation of multiple subsurface laser damage patterns including groups of parallel lines that are non-parallel to one another, but with each line remaining within ±5 degrees of perpendicular to the <1120> direction of a hexagonal crystal structure of a material of the substrate. Further methods involve formation of initial and subsequent subsurface laser damage patterns that are centered at different depths within an interior of a substrate, with the subsurface laser damage patterns being registered with one another and having vertical extents that are overlapping.

A Taiko wafer ring cut process method is provided. The Taiko wafer ring cut process method includes the following steps. A Taiko wafer is disposed on the platform. The Taiko wafer is performing by laser ring cutting so that a Taiko ring and an edge portion of the Taiko wafer are separated from a wafer portion of the Taiko wafer. The wafer portion of the Taiko wafer is adhered to a frame.

A substrate processing system configured to process a substrate includes an eccentricity detection device configured to detect, in a combined substrate in which a first substrate and a second substrate are bonded to each other, an eccentricity of the first substrate; a modification layer forming device configured to form a modification layer within the first substrate along a boundary between a peripheral portion to be removed and a central portion of the first substrate; and a periphery removing device configured to remove the peripheral portion starting from the modification layer.

A silicon carbide substrate has a first main surface, a second main surface, and a chamfered portion. The second main surface is opposite to the first main surface. The chamfered portion is contiguous to each of the first main surface and the second main surface. The silicon carbide substrate has a maximum diameter of 150 mm or more. A surface manganese concentration in the chamfered portion is 1×10.sup.11 atoms/cm.sup.2 or less.

A silicon carbide substrate in accordance with the present disclosure includes a main surface. The silicon carbide substrate has a maximum diameter of 150 mm or more. In the main surface, a total area of a region in which a concentration of each of sodium, aluminum, potassium, calcium, titanium, iron, copper, and zinc is less than 5×10.sup.10 atoms/cm.sup.2 is more than or equal to 95% of an area of the main surface.